soc/intel/xeon_sp/acpi.c: Add ACPI C-State table

Add the soc ACPI _CST table.
The table may be customized to support the different state
combinations and set by the mainboard config.

Tested on deltalake with acpi_idle driver.
Note, intel_idle may not use ACPI _CST table.

Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
This commit is contained in:
Marc Jones 2021-01-15 13:29:14 -07:00 committed by Patrick Georgi
parent 08de06ad6d
commit 31ed8856f9
5 changed files with 103 additions and 2 deletions

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@ -6,10 +6,86 @@
#include <soc/util.h>
#include <string.h>
#include "chip.h"
/*
* List of supported C-states in this processor.
*/
enum {
C_STATE_C1, /* 0 */
C_STATE_C3, /* 1 */
C_STATE_C6, /* 2 */
C_STATE_C7, /* 3 */
NUM_C_STATES
};
static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
[C_STATE_C1] = {
/* C1 */
.latency = 1,
.power = 0x3e8,
.resource = MWAIT_RES(0, 0),
},
[C_STATE_C3] = {
/* C3 */
.latency = 15,
.power = 0x1f4,
.resource = MWAIT_RES(1, 0),
},
[C_STATE_C6] = {
/* C6 */
.latency = 41,
.power = 0x15e,
.resource = MWAIT_RES(2, 0),
},
[C_STATE_C7] = {
/* C7 */
.latency = 41,
.power = 0x0c8,
.resource = MWAIT_RES(3, 0),
}
};
/* Max states supported */
static int cstate_set_all[] = {
C_STATE_C1,
C_STATE_C3,
C_STATE_C6,
C_STATE_C7
};
static int cstate_set_c1_c6[] = {
C_STATE_C1,
C_STATE_C6,
};
acpi_cstate_t *soc_get_cstate_map(size_t *entries)
{
*entries = 0;
return NULL;
static acpi_cstate_t map[ARRAY_SIZE(cstate_set_all)];
int *cstate_set;
int i;
const config_t *config = config_of_soc();
const enum acpi_cstate_mode states = config->cstate_states;
switch (states) {
case CSTATES_C1C6:
*entries = ARRAY_SIZE(cstate_set_c1_c6);
cstate_set = cstate_set_c1_c6;
break;
case CSTATES_ALL:
default:
*entries = ARRAY_SIZE(cstate_set_all);
cstate_set = cstate_set_all;
break;
}
for (i = 0; i < *entries; i++) {
map[i] = cstate_map[cstate_set[i]];
map[i].ctype = i + 1;
}
return map;
}
static void print_madt_ioapic(int socket, int stack,

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@ -4,6 +4,7 @@
#define _SOC_CHIP_H_
#include <intelblocks/cfg.h>
#include <soc/acpi.h>
#include <soc/gpio.h>
#include <soc/irq.h>
#include <stdint.h>
@ -96,6 +97,8 @@ struct soc_intel_xeon_sp_cpx_config {
/* TCC activation offset */
uint32_t tcc_offset;
enum acpi_cstate_mode cstate_states;
};
typedef struct soc_intel_xeon_sp_cpx_config config_t;

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@ -98,8 +98,19 @@
#define XHCI_BUS_NUMBER 0x0
#define PCH_DEV_SLOT_XHCI 0x14
#define XHCI_FUNC_NUM 0x0
#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
#define PCH_DEV_SLOT_CSE 0x16
#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
#define PCH_DEV_SLOT_LPC 0x1f
#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)

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@ -5,6 +5,14 @@
#include <acpi/acpi.h>
/**
Select C-state map set in config cstate_states
**/
enum acpi_cstate_mode {
CSTATES_ALL = 0,
CSTATES_C1C6
};
#define MEM_BLK_COUNT 0x140
typedef struct {
uint8_t buf[32];

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@ -5,6 +5,7 @@
#include <stdint.h>
#include <intelblocks/cfg.h>
#include <soc/acpi.h>
#include <soc/gpio.h>
#include <soc/irq.h>
@ -73,6 +74,8 @@ struct soc_intel_xeon_sp_skx_config {
/* TCC activation offset */
uint32_t tcc_offset;
enum acpi_cstate_mode cstate_states;
};
typedef struct soc_intel_xeon_sp_skx_config config_t;