soc/intel/xeon_sp/acpi.c: Add ACPI C-State table
Add the soc ACPI _CST table. The table may be customized to support the different state combinations and set by the mainboard config. Tested on deltalake with acpi_idle driver. Note, intel_idle may not use ACPI _CST table. Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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@ -6,10 +6,86 @@
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#include <soc/util.h>
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#include <string.h>
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#include "chip.h"
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/*
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* List of supported C-states in this processor.
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*/
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enum {
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C_STATE_C1, /* 0 */
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C_STATE_C3, /* 1 */
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C_STATE_C6, /* 2 */
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C_STATE_C7, /* 3 */
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NUM_C_STATES
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};
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static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
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[C_STATE_C1] = {
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/* C1 */
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.latency = 1,
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.power = 0x3e8,
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.resource = MWAIT_RES(0, 0),
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},
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[C_STATE_C3] = {
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/* C3 */
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.latency = 15,
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.power = 0x1f4,
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.resource = MWAIT_RES(1, 0),
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},
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[C_STATE_C6] = {
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/* C6 */
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.latency = 41,
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.power = 0x15e,
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.resource = MWAIT_RES(2, 0),
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},
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[C_STATE_C7] = {
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/* C7 */
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.latency = 41,
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.power = 0x0c8,
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.resource = MWAIT_RES(3, 0),
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}
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};
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/* Max states supported */
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static int cstate_set_all[] = {
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C_STATE_C1,
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C_STATE_C3,
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C_STATE_C6,
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C_STATE_C7
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};
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static int cstate_set_c1_c6[] = {
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C_STATE_C1,
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C_STATE_C6,
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};
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acpi_cstate_t *soc_get_cstate_map(size_t *entries)
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{
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*entries = 0;
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return NULL;
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static acpi_cstate_t map[ARRAY_SIZE(cstate_set_all)];
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int *cstate_set;
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int i;
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const config_t *config = config_of_soc();
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const enum acpi_cstate_mode states = config->cstate_states;
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switch (states) {
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case CSTATES_C1C6:
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*entries = ARRAY_SIZE(cstate_set_c1_c6);
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cstate_set = cstate_set_c1_c6;
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break;
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case CSTATES_ALL:
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default:
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*entries = ARRAY_SIZE(cstate_set_all);
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cstate_set = cstate_set_all;
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break;
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}
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for (i = 0; i < *entries; i++) {
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map[i] = cstate_map[cstate_set[i]];
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map[i].ctype = i + 1;
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}
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return map;
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}
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static void print_madt_ioapic(int socket, int stack,
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@ -4,6 +4,7 @@
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#define _SOC_CHIP_H_
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#include <intelblocks/cfg.h>
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#include <soc/acpi.h>
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#include <soc/gpio.h>
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#include <soc/irq.h>
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#include <stdint.h>
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@ -96,6 +97,8 @@ struct soc_intel_xeon_sp_cpx_config {
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/* TCC activation offset */
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uint32_t tcc_offset;
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enum acpi_cstate_mode cstate_states;
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};
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typedef struct soc_intel_xeon_sp_cpx_config config_t;
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@ -98,8 +98,19 @@
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#define XHCI_BUS_NUMBER 0x0
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#define PCH_DEV_SLOT_XHCI 0x14
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#define XHCI_FUNC_NUM 0x0
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#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
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#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
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#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
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#define PCH_DEV_SLOT_CSE 0x16
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#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
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#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
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#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
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#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
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#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
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#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
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#define PCH_DEV_SLOT_LPC 0x1f
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#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
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#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
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@ -5,6 +5,14 @@
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#include <acpi/acpi.h>
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/**
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Select C-state map set in config cstate_states
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**/
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enum acpi_cstate_mode {
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CSTATES_ALL = 0,
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CSTATES_C1C6
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};
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#define MEM_BLK_COUNT 0x140
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typedef struct {
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uint8_t buf[32];
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@ -5,6 +5,7 @@
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#include <stdint.h>
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#include <intelblocks/cfg.h>
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#include <soc/acpi.h>
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#include <soc/gpio.h>
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#include <soc/irq.h>
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@ -73,6 +74,8 @@ struct soc_intel_xeon_sp_skx_config {
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/* TCC activation offset */
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uint32_t tcc_offset;
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enum acpi_cstate_mode cstate_states;
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};
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typedef struct soc_intel_xeon_sp_skx_config config_t;
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