vc/amd/fsp: Add UPD header files for picasso
Add files for Picasso's FSP UPD definitions. These are automatically generated from the FSP build. Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34575 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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/** @file
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*
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* This file is automatically generated.
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*
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*/
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#ifdef EFI32
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# include <FspEas.h>
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# include <stdint.h>
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#else
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# include <fsp_h_c99.h>
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#endif
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#define FSPM_UPD_SIGNATURE 0x4D5F4f5341434950 /* 'PICASO_M' */
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#define FSPS_UPD_SIGNATURE 0x535F4f5341434950 /* 'PICASO_S' */
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#endif
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/** @file
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*
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* This file is automatically generated.
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*
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*/
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#ifndef __FSPMUPD_H__
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#define __FSPMUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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/** Fsp M Configuration
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**/
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typedef struct {
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/** Offset 0x0040**/ uint32_t pci_express_base_addr;
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/** Offset 0x0044**/ uint32_t serial_port_base;
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/** Offset 0x0048**/ uint32_t serial_port_use_mmio;
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/** Offset 0x004C**/ uint32_t serial_port_stride;
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/** Offset 0x0050**/ uint32_t serial_port_baudrate;
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/** Offset 0x0054**/ uint32_t serial_port_refclk;
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/** Offset 0x0058**/ uint8_t UnusedUpdSpace0[168];
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/** Offset 0x0100**/ uint16_t Reserved100;
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/** Offset 0x0102**/ uint16_t UpdTerminator;
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} FSP_M_CONFIG;
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/** Fsp M UPD Configuration
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**/
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typedef struct {
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/** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
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/** Offset 0x0020**/ FSPM_ARCH_UPD FspmArchUpd;
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/** Offset 0x0040**/ FSP_M_CONFIG FspmConfig;
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} FSPM_UPD;
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#pragma pack()
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#endif
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/** @file
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*
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* This file is automatically generated.
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*
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*/
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#ifndef __FSPSUPD_H__
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#define __FSPSUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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typedef struct {
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/** Offset 0x0020**/ uint32_t pcie_port0_topology;
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/** Offset 0x0024**/ uint32_t pcie_port1_topology;
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/** Offset 0x0028**/ uint32_t pcie_port2_topology;
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/** Offset 0x002C**/ uint32_t pcie_port3_topology;
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/** Offset 0x0030**/ uint32_t pcie_port4_topology;
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/** Offset 0x0034**/ uint32_t pcie_port5_topology;
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/** Offset 0x0038**/ uint32_t pcie_port6_topology;
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/** Offset 0x003C**/ uint32_t pcie_sata_topology;
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/** Offset 0x0040**/ uint32_t pcie_xgbe1_topology;
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/** Offset 0x0044**/ uint32_t pcie_xgbe2_topology;
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/** Offset 0x0048**/ uint32_t dp0_connector_type;
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/** Offset 0x004C**/ uint32_t dp1_connector_type;
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/** Offset 0x0050**/ uint32_t dp2_connector_type;
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/** Offset 0x0054**/ uint32_t dp3_connector_type;
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/** Offset 0x0058**/ uint32_t emmc0_mode;
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/** Offset 0x005C**/ uint8_t UnusedUpdSpace0[196];
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/** Offset 0x0120**/ uint16_t UpdTerminator;
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} FSP_S_CONFIG;
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/** Fsp S UPD Configuration
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**/
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typedef struct {
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/** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
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/** Offset 0x0020**/ FSP_S_CONFIG FspsConfig;
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} FSPS_UPD;
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#pragma pack()
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#endif
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/** @file
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*
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* C99 common FSP definitions from
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* Intel Firmware Support Package External Architecture Specification v2.0
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*
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* These definitions come in a format that is usable outside an EFI environment.
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**/
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#ifndef FSP_H_C99_H
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#define FSP_H_C99_H
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#include <stdint.h>
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enum {
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FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001,
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FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002,
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FSP_STATUS_RESET_REQUIRED_3 = 0x40000003,
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FSP_STATUS_RESET_REQUIRED_4 = 0x40000004,
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FSP_STATUS_RESET_REQUIRED_5 = 0x40000005,
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FSP_STATUS_RESET_REQUIRED_6 = 0x40000006,
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FSP_STATUS_RESET_REQUIRED_7 = 0x40000007,
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FSP_STATUS_RESET_REQUIRED_8 = 0x40000008,
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};
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typedef enum {
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EnumInitPhaseAfterPciEnumeration = 0x20,
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EnumInitPhaseReadyToBoot = 0x40,
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EnumInitPhaseEndOfFirmware = 0xF0
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} FSP_INIT_PHASE;
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typedef struct {
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uint64_t Signature;
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uint8_t Revision;
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uint8_t Reserved[23];
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} FSP_UPD_HEADER;
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_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
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typedef struct {
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uint8_t Revision;
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uint8_t Reserved[3];
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void *NvsBufferPtr;
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void *StackBase;
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uint32_t StackSize;
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uint32_t BootLoaderTolumSize;
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uint32_t BootMode;
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uint8_t Reserved1[8];
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} FSPM_ARCH_UPD;
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_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
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#endif /* FSP_H_C99_H */
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