vc/amd/fsp: Add UPD header files for picasso

Add files for Picasso's FSP UPD definitions.  These are automatically
generated from the FSP build.

Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34575
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/amd/fsp/picasso/FspUpd.h

@@ -0,0 +1,22 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#ifdef EFI32
+# include <FspEas.h>
+# include <stdint.h>
+#else
+# include <fsp_h_c99.h>
+#endif
+
+#define FSPM_UPD_SIGNATURE               0x4D5F4f5341434950        /* 'PICASO_M' */
+
+#define FSPS_UPD_SIGNATURE               0x535F4f5341434950        /* 'PICASO_S' */
+
+
+#endif

src/vendorcode/amd/fsp/picasso/FspmUpd.h

@@ -0,0 +1,39 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+	/** Offset 0x0040**/	uint32_t                    pci_express_base_addr;
+	/** Offset 0x0044**/	uint32_t                    serial_port_base;
+	/** Offset 0x0048**/	uint32_t                    serial_port_use_mmio;
+	/** Offset 0x004C**/	uint32_t                    serial_port_stride;
+	/** Offset 0x0050**/	uint32_t                    serial_port_baudrate;
+	/** Offset 0x0054**/	uint32_t                    serial_port_refclk;
+	/** Offset 0x0058**/	uint8_t                     UnusedUpdSpace0[168];
+	/** Offset 0x0100**/	uint16_t                    Reserved100;
+	/** Offset 0x0102**/	uint16_t                    UpdTerminator;
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+	/** Offset 0x0000**/	FSP_UPD_HEADER              FspUpdHeader;
+	/** Offset 0x0020**/	FSPM_ARCH_UPD               FspmArchUpd;
+	/** Offset 0x0040**/	FSP_M_CONFIG                FspmConfig;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif

src/vendorcode/amd/fsp/picasso/FspsUpd.h

@@ -0,0 +1,44 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+typedef struct {
+	/** Offset 0x0020**/	uint32_t                    pcie_port0_topology;
+	/** Offset 0x0024**/	uint32_t                    pcie_port1_topology;
+	/** Offset 0x0028**/	uint32_t                    pcie_port2_topology;
+	/** Offset 0x002C**/	uint32_t                    pcie_port3_topology;
+	/** Offset 0x0030**/	uint32_t                    pcie_port4_topology;
+	/** Offset 0x0034**/	uint32_t                    pcie_port5_topology;
+	/** Offset 0x0038**/	uint32_t                    pcie_port6_topology;
+	/** Offset 0x003C**/	uint32_t                    pcie_sata_topology;
+	/** Offset 0x0040**/	uint32_t                    pcie_xgbe1_topology;
+	/** Offset 0x0044**/	uint32_t                    pcie_xgbe2_topology;
+	/** Offset 0x0048**/	uint32_t                    dp0_connector_type;
+	/** Offset 0x004C**/	uint32_t                    dp1_connector_type;
+	/** Offset 0x0050**/	uint32_t                    dp2_connector_type;
+	/** Offset 0x0054**/	uint32_t                    dp3_connector_type;
+	/** Offset 0x0058**/	uint32_t                    emmc0_mode;
+	/** Offset 0x005C**/	uint8_t                     UnusedUpdSpace0[196];
+	/** Offset 0x0120**/	uint16_t                    UpdTerminator;
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+	/** Offset 0x0000**/	FSP_UPD_HEADER              FspUpdHeader;
+	/** Offset 0x0020**/	FSP_S_CONFIG                FspsConfig;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif

src/vendorcode/amd/fsp/picasso/fsp_h_c99.h

@@ -0,0 +1,51 @@
+/** @file
+ *
+ * C99 common FSP definitions from
+ * Intel Firmware Support Package External Architecture Specification v2.0
+ *
+ * These definitions come in a format that is usable outside an EFI environment.
+ **/
+#ifndef FSP_H_C99_H
+#define FSP_H_C99_H
+
+#include <stdint.h>
+
+enum {
+	FSP_STATUS_RESET_REQUIRED_COLD		= 0x40000001,
+	FSP_STATUS_RESET_REQUIRED_WARM		= 0x40000002,
+	FSP_STATUS_RESET_REQUIRED_3		= 0x40000003,
+	FSP_STATUS_RESET_REQUIRED_4		= 0x40000004,
+	FSP_STATUS_RESET_REQUIRED_5		= 0x40000005,
+	FSP_STATUS_RESET_REQUIRED_6		= 0x40000006,
+	FSP_STATUS_RESET_REQUIRED_7		= 0x40000007,
+	FSP_STATUS_RESET_REQUIRED_8		= 0x40000008,
+};
+
+typedef enum {
+	EnumInitPhaseAfterPciEnumeration	= 0x20,
+	EnumInitPhaseReadyToBoot		= 0x40,
+	EnumInitPhaseEndOfFirmware		= 0xF0
+} FSP_INIT_PHASE;
+
+typedef struct {
+	uint64_t	Signature;
+	uint8_t		Revision;
+	uint8_t		Reserved[23];
+} FSP_UPD_HEADER;
+
+_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
+
+typedef struct {
+	uint8_t		Revision;
+	uint8_t		Reserved[3];
+	void		*NvsBufferPtr;
+	void		*StackBase;
+	uint32_t	StackSize;
+	uint32_t	BootLoaderTolumSize;
+	uint32_t	BootMode;
+	uint8_t		Reserved1[8];
+} FSPM_ARCH_UPD;
+
+_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
+
+#endif /* FSP_H_C99_H */