AGESA S3: Refactor S3 backup store locations in SPI
Prepare code to locate S3 backup from CBFS as a file. Follow-up will replace remaining use of CONFIG_S3_DATA_POS with cbfs_get_file_content(). Change-Id: I693c41c90e61d1a7c7b10e43c9f264d099c9a400 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6083 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
This commit is contained in:
Kyösti Mälkki
parent
2093c4f7c2
commit
31eff28f4f
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@ -39,14 +39,53 @@
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#include <spi_flash.h>
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#endif
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/* The size needs to be 4k aligned, which is the sector size of most flashes. */
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#define S3_DATA_VOLATILE_SIZE 0x6000
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#define S3_DATA_MTRR_SIZE 0x1000
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#define S3_DATA_NONVOLATILE_SIZE 0x1000
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#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
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(S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE
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#error "Please increase the value of S3_DATA_SIZE"
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#endif
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static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
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{
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/* FIXME: Find file from CBFS. */
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u32 s3_data = CONFIG_S3_DATA_POS;
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switch (S3DataType) {
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case S3DataTypeVolatile:
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*pos = s3_data;
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*len = S3_DATA_VOLATILE_SIZE;
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break;
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case S3DataTypeMTRR:
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*pos = s3_data + S3_DATA_VOLATILE_SIZE;
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*len = S3_DATA_MTRR_SIZE;
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break;
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case S3DataTypeNonVolatile:
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*pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE;
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*len = S3_DATA_NONVOLATILE_SIZE;
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break;
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default:
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*pos = 0;
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*len = 0;
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break;
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}
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}
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void restore_mtrr(void)
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{
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u32 msr;
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volatile UINT32 *msrPtr = (volatile UINT32 *)S3_DATA_MTRR_POS;
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volatile UINT32 *msrPtr;
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msr_t msr_data;
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printk(BIOS_SPEW, "%s\n", __func__);
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u32 pos, size;
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get_s3nv_data(S3DataTypeMTRR, &pos, &size);
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msrPtr = (UINT32 *)pos;
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disable_cache();
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/* Enable access to AMD RdDram and WrDram extension bits */
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@ -136,7 +175,7 @@ void move_stack_high_mem(void)
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}
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#ifndef __PRE_RAM__
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void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx)
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static void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx)
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{
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msr_t msr_data;
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msr_data = rdmsr(idx);
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@ -157,10 +196,12 @@ void OemAgesaSaveMtrr(void)
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{
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#ifndef __PRE_RAM__
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msr_t msr_data;
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u32 nvram_pos = S3_DATA_MTRR_POS;
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u32 i;
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struct spi_flash *flash;
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u32 pos, size;
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get_s3nv_data(S3DataTypeMTRR, &pos, &size);
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spi_init();
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flash = spi_flash_probe(0, 0, 0, 0);
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@ -172,7 +213,8 @@ void OemAgesaSaveMtrr(void)
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flash->spi->rw = SPI_WRITE_FLAG;
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spi_claim_bus(flash->spi);
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flash->erase(flash, S3_DATA_MTRR_POS, S3_DATA_MTRR_SIZE);
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flash->erase(flash, pos, size);
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u32 nvram_pos = pos;
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/* Enable access to AMD RdDram and WrDram extension bits */
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msr_data = rdmsr(SYS_CFG);
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@ -212,31 +254,30 @@ void OemAgesaSaveMtrr(void)
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void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data)
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{
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AMD_CONFIG_PARAMS StdHeader;
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u32 pos, size;
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get_s3nv_data(S3DataType, &pos, &size);
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if (S3DataType == S3DataTypeNonVolatile) {
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*Data = (void *)S3_DATA_NONVOLATILE_POS;
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*DataSize = *(UINTN *) (*Data);
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*Data += 4;
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} else {
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*DataSize = *(UINTN *) S3_DATA_VOLATILE_POS;
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*Data = (void *) GetHeapBase(&StdHeader);
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memcpy((void *)(*Data), (void *)(S3_DATA_VOLATILE_POS + 4), *DataSize);
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*DataSize = *(UINT32 *) pos;
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*Data = (void *) (pos + sizeof(UINT32));
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} else if (S3DataType == S3DataTypeVolatile) {
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u32 len = *(UINT32 *) pos;
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void *src = (void *) (pos + sizeof(UINT32));
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void *dst = (void *) GetHeapBase(&StdHeader);
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memcpy(dst, src, len);
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*DataSize = len;
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*Data = dst;
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}
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}
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#ifndef __PRE_RAM__
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u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
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{
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u32 pos = S3_DATA_VOLATILE_POS;
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u32 data;
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u32 nvram_pos;
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struct spi_flash *flash;
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if (S3DataType == S3DataTypeNonVolatile) {
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pos = S3_DATA_NONVOLATILE_POS;
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} else { /* S3DataTypeVolatile */
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pos = S3_DATA_VOLATILE_POS;
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}
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u32 pos, size;
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get_s3nv_data(S3DataType, &pos, &size);
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spi_init();
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flash = spi_flash_probe(0, 0, 0, 0);
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@ -249,17 +290,11 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
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flash->spi->rw = SPI_WRITE_FLAG;
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spi_claim_bus(flash->spi);
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if (S3DataType == S3DataTypeNonVolatile) {
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flash->erase(flash, S3_DATA_NONVOLATILE_POS, S3_DATA_NONVOLATILE_SIZE);
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} else {
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flash->erase(flash, S3_DATA_VOLATILE_POS, S3_DATA_VOLATILE_SIZE);
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}
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nvram_pos = 0;
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flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize);
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flash->erase(flash, pos, size);
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flash->write(flash, pos, sizeof(DataSize), &DataSize);
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u32 nvram_pos;
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for (nvram_pos = 0; nvram_pos < DataSize - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) {
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data = *(u32 *) (Data + nvram_pos);
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flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos));
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}
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flash->write(flash, nvram_pos + pos + 4, DataSize % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos));
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@ -20,22 +20,10 @@
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#ifndef S3_RESUME_H
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#define S3_RESUME_H
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/* The size needs to be 4k aligned, which is the sector size of most flashes. */
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#define S3_DATA_VOLATILE_SIZE 0x6000
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#define S3_DATA_MTRR_SIZE 0x1000
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#define S3_DATA_NONVOLATILE_SIZE 0x1000
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#define S3_DATA_VOLATILE_POS CONFIG_S3_DATA_POS
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#define S3_DATA_MTRR_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE)
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#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE)
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#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
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(S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE
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#error "Please increase the value of S3_DATA_SIZE"
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#endif
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typedef enum {
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S3DataTypeNonVolatile=0, ///< NonVolatile Data Type
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S3DataTypeVolatile ///< Volatile Data Type
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S3DataTypeNonVolatile=0, ///< NonVolatile Data Type
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S3DataTypeVolatile, ///< Volatile Data Type
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S3DataTypeMTRR ///< MTRR storage
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} S3_DATA_TYPE;
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void restore_mtrr(void);
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@ -48,9 +36,4 @@ u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
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void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
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void OemAgesaSaveMtrr (void);
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#ifndef __PRE_RAM__
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#include <spi_flash.h>
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void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx);
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#endif
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#endif
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