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mb/google/brya: Enable S0ix 

This change enables S0ix for brya platform.

BUG=b:181843816
TEST=Built image and booted to kernel.

Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sugnan Prabhu S 2021-03-16 18:05:13 +05:30 committed by Patrick Georgi
parent 9f5261e5fa
commit 31f383686a
1 changed files with 3 additions and 0 deletions
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src/mainboard/google/brya/variants/baseboard/devicetree.cb
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@ -14,6 +14,9 @@ chip soc/intel/alderlake
# EC memory map range is 0x900-0x9ff # EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901" register "gen3_dec" = "0x00fc0901"
# S0ix enable
register "s0ix_enable" = "1"
# This disabled autonomous GPIO power management, otherwise # This disabled autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses; need to clarify # old cr50 FW only supports short pulses; need to clarify
# the minimum PCH IRQ pulse width with Intel, b/180111628 # the minimum PCH IRQ pulse width with Intel, b/180111628