From 31f502a6be09aee21dfca92b0400f17e5f47c045 Mon Sep 17 00:00:00 2001 From: Shon Wang Date: Fri, 7 Apr 2023 15:19:51 +0800 Subject: [PATCH] mb/google/nissa/var/yaviks: Update GPIOs to support yavilla Yavilla is a variant of yaviks which is almost identical to yaviks, so is reusing the yaviks coreboot variant. so update the GPIO tables to handle these based on fw_config. BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I831b199055c931e7a4a393eeb9e75e83c8ae3c3a Signed-off-by: Shon Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/74264 Reviewed-by: Derek Huang Tested-by: build bot (Jenkins) --- .../google/brya/variants/yaviks/fw_config.c | 28 ++++++ .../google/brya/variants/yaviks/gpio.c | 85 +++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/src/mainboard/google/brya/variants/yaviks/fw_config.c b/src/mainboard/google/brya/variants/yaviks/fw_config.c index 800fc1f205..b3de0fd642 100644 --- a/src/mainboard/google/brya/variants/yaviks/fw_config.c +++ b/src/mainboard/google/brya/variants/yaviks/fw_config.c @@ -5,6 +5,17 @@ #include #include +static const struct pad_config lte_disable_pads_yavilla[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC(GPP_F12, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + static const struct pad_config emmc_disable_pads[] = { /* I7 : EMMC_CMD */ PAD_NC(GPP_I7, NONE), @@ -32,6 +43,13 @@ static const struct pad_config emmc_disable_pads[] = { PAD_NC(GPP_I18, NONE), }; +static const struct pad_config stylus_disable_pads[] = { + /* F13 : SOC_PEN_DETECT_R_ODL */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : SOC_PEN_DETECT_ODL */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), +}; + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { @@ -39,4 +57,14 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) gpio_padbased_override(padbased_table, emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads)); } + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins on yavilla.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads_yavilla, + ARRAY_SIZE(lte_disable_pads_yavilla)); + } + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { + printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); + gpio_padbased_override(padbased_table, stylus_disable_pads, + ARRAY_SIZE(stylus_disable_pads)); + } } diff --git a/src/mainboard/google/brya/variants/yaviks/gpio.c b/src/mainboard/google/brya/variants/yaviks/gpio.c index b6f95dd1d3..240d01221b 100644 --- a/src/mainboard/google/brya/variants/yaviks/gpio.c +++ b/src/mainboard/google/brya/variants/yaviks/gpio.c @@ -4,6 +4,7 @@ #include #include #include +#include /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { @@ -57,6 +58,47 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_R7, NONE), }; +/* Pad configuration in ramstage for yavilla */ +static const struct pad_config override_gpio_table_yavilla[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A18 : NC ==> HDMI_HPD_SRC */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), + /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* D6 : WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D8 : SD_CLKREQ_ODL ==> NC */ + PAD_NC(GPP_D8, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F12 : WWAN_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* F23 : V1P05EXT_CTRL ==> NC */ + PAD_NC(GPP_F23, NONE), + + /* H8 : CNV_MFUART2_RXD ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : CNV_MFUART2_TXD ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : SD_PERST_L ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : EN_PP3300_SD_X ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H15 : HDMI_SRC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : HDMI_SRC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), +}; + /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* H12 : UART0_RTS# ==> SD_PERST_L */ @@ -83,6 +125,32 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_H13, 1, DEEP), }; +/* Early pad configuration in bootblock for yavilla */ +static const struct pad_config early_gpio_table_yavilla[] = { + /* D6 : WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 0, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + /* F12 : WWAN_RST_ODL */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), +}; + static const struct pad_config romstage_gpio_table[] = { /* H12 : UART0_RTS# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H12, 1, DEEP), @@ -90,20 +158,37 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_H20, 1, DEEP), }; +static const struct pad_config romstage_gpio_table_yavilla[] = { + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C)) || fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + *num = ARRAY_SIZE(override_gpio_table_yavilla); + return override_gpio_table_yavilla; + } *num = ARRAY_SIZE(override_gpio_table); return override_gpio_table; } const struct pad_config *variant_early_gpio_table(size_t *num) { + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C)) || fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + *num = ARRAY_SIZE(early_gpio_table_yavilla); + return early_gpio_table_yavilla; + } *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } const struct pad_config *variant_romstage_gpio_table(size_t *num) { + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C)) || fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + *num = ARRAY_SIZE(romstage_gpio_table_yavilla); + return romstage_gpio_table_yavilla; + } *num = ARRAY_SIZE(romstage_gpio_table); return romstage_gpio_table; }