mb/google/poppy/variants/nami: Update DPTF table from version 1.5
Update dptf.asl and TCC parameters from tuning of the thermal team. BUG=b:72974136 TEST=Match the result from DPTF UI Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27086 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -282,7 +282,7 @@ chip soc/intel/skylake
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register "speed_shift_enable" = "1"
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register "speed_shift_enable" = "1"
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register "tcc_offset" = "10" # TCC of 90C
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register "tcc_offset" = "3" # TCC of 97C
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register "psys_pmax" = "101"
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register "psys_pmax" = "101"
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# PCH Trip Temperature in degree C
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# PCH Trip Temperature in degree C
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@ -23,23 +23,23 @@
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "Thermal_Sensor_Remote_CPU"
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#define DPTF_TSR0_SENSOR_NAME "Thermal_Sensor_Remote_CPU"
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#define DPTF_TSR0_PASSIVE 81
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#define DPTF_TSR0_PASSIVE 75
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#define DPTF_TSR0_CRITICAL 125
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#define DPTF_TSR0_CRITICAL 125
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#define DPTF_TSR0_ACTIVE_AC0 50
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#define DPTF_TSR0_ACTIVE_AC0 50
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#define DPTF_TSR0_ACTIVE_AC1 47
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#define DPTF_TSR0_ACTIVE_AC1 47
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#define DPTF_TSR0_ACTIVE_AC2 45
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#define DPTF_TSR0_ACTIVE_AC2 45
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#define DPTF_TSR0_ACTIVE_AC3 43
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#define DPTF_TSR0_ACTIVE_AC3 42
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#define DPTF_TSR0_ACTIVE_AC4 41
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#define DPTF_TSR0_ACTIVE_AC4 39
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "Thermal_Sensor_Remote_PMIC"
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#define DPTF_TSR1_SENSOR_NAME "Thermal_Sensor_Remote_PMIC"
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#define DPTF_TSR1_PASSIVE 78
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#define DPTF_TSR1_PASSIVE 75
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#define DPTF_TSR1_CRITICAL 125
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#define DPTF_TSR1_CRITICAL 125
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#define DPTF_TSR1_ACTIVE_AC0 50
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#define DPTF_TSR1_ACTIVE_AC0 50
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#define DPTF_TSR1_ACTIVE_AC1 47
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#define DPTF_TSR1_ACTIVE_AC1 47
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#define DPTF_TSR1_ACTIVE_AC2 45
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#define DPTF_TSR1_ACTIVE_AC2 45
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#define DPTF_TSR1_ACTIVE_AC3 43
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#define DPTF_TSR1_ACTIVE_AC3 42
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#define DPTF_TSR1_ACTIVE_AC4 41
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#define DPTF_TSR1_ACTIVE_AC4 39
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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#define DPTF_ENABLE_FAN_CONTROL
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@ -63,7 +63,7 @@ Name (DFPS, Package () {
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/* Control, Trip Point, Speed, NoiseLevel, Power */
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/* Control, Trip Point, Speed, NoiseLevel, Power */
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Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
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Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
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Package () {69, 0xFFFFFFFF, 5800, 180, 1800},
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Package () {69, 0xFFFFFFFF, 5800, 180, 1800},
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Package () {52, 0xFFFFFFFF, 5000, 145, 1450},
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Package () {56, 0xFFFFFFFF, 5000, 145, 1450},
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Package () {46, 0xFFFFFFFF, 4900, 115, 1150},
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Package () {46, 0xFFFFFFFF, 4900, 115, 1150},
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Package () {36, 0xFFFFFFFF, 3900, 90, 900}
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Package () {36, 0xFFFFFFFF, 3900, 90, 900}
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})
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})
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@ -76,15 +76,15 @@ Name (DART, Package () {
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* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
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* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
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* AC7, AC8, AC9
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* AC7, AC8, AC9
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*/
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*/
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\_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 90, 69, 52, 46, 36, 0, 0,
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\_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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0, 0, 0
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},
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},
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Package () {
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 52, 46, 36, 0, 0,
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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0, 0, 0
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},
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},
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Package () {
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 52, 46, 36, 0, 0,
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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0, 0, 0
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}
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}
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})
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})
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