Drop northbridge/i440lx
All boards using it have been deleted a long time ago. Change-Id: Ib1c4018ab6ec27868c0e2fdbf9c91323ead076fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12236 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer
parent
ac901e6bed
commit
31ff120a2c
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@ -1,23 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
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||||
##
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||||
## This program is distributed in the hope that it will be useful,
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||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
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||||
##
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||||
## You should have received a copy of the GNU General Public License
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||||
## along with this program; if not, write to the Free Software
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||||
## Foundation, Inc.
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##
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config NORTHBRIDGE_INTEL_I440LX
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bool
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select HAVE_DEBUG_RAM_SETUP
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select LATE_CBMEM_INIT
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@ -1,25 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
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||||
##
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||||
## This program is distributed in the hope that it will be useful,
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||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
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||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc.
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##
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440LX),y)
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ramstage-y += northbridge.c
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endif
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@ -1,72 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Maciej Pijanka <maciej.pijanka@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
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||||
* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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||||
*
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||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
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||||
*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
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*/
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/*
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* Datasheet:
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* - Name: Intel 440LX AGPset: 82443LX Host Bridge/Controller
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* - PDF: 29056402.pdf
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*/
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/*
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* Host-to-PCI Bridge Registers.
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* The values in parenthesis are the default values as per datasheet.
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* Any addresses between 0x00 and 0xff not listed below are either
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*
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* i didnt listed every register that IS implemented, just usefull ones
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* -- Maciej `agaran` Pijanka
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*
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* Reserved or Intel Reserved and should not be touched.
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*/
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#define APBASE 0x34 /* Aperture Base Address (0x00000008) */
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#define PACCFG 0x50 /* 440LX PAC Configuration Register (0s00_s000_0000_0s00b) */
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#define DBC 0x53 /* DRAM Row Type Register (0x83) */
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#define DRT 0x55 /* DRAM Row Type Register (0x0000) */
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#define DRAMC 0x57 /* DRAM Control (0x01) */
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#define DRAMT 0x58 /* DRAM Timing (0x00) */
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#define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */
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#define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */
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#define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */
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#define DRAMXC 0x6A /* Dram Extended Control Register (0x0000) */
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#define MBSC 0x6C /* Memory Buffer Strength Control: (0x55555555) */
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#define SMRAM 0x72 /* System Management RAM Control (0x02). */
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#define ERRCMD 0x90 /* Error Command Register (0x80). */
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#define ERRSTS0 0x91 /* Error Status (0x0000). */
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#define ERRSTS1 0x92 /* Error Status (0x0000). */
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// TODO: AGP stuff.
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/* For convenience: */
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#define DRB0 0x60
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#define DRB1 0x61
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#define DRB2 0x62
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#define DRB3 0x63
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#define DRB4 0x64
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#define DRB5 0x65
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#define DRB6 0x66
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#define DRB7 0x67
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#define PAM0 0x59
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#define PAM1 0x5a
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#define PAM2 0x5b
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#define PAM3 0x5c
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#define PAM4 0x5d
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#define PAM5 0x5e
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#define PAM6 0x5f
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@ -1,137 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Maciej Pijanka <maciej.pijanka@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc.
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <string.h>
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#include <cbmem.h>
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#include <cpu/cpu.h>
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#include <pc80/keyboard.h>
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#include "northbridge.h"
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#include "i440lx.h"
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/* This code is mostly same as 440BX created by Uwe Hermann,
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* i done only very minor changes like renamed functions to 440lx etc
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* Maciej
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*/
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static void northbridge_init(device_t dev)
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{
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printk(BIOS_SPEW, "Northbridge Init\n");
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}
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static struct device_operations northbridge_operations = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = northbridge_init,
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.enable = 0,
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.ops_pci = 0,
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};
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static const struct pci_driver northbridge_driver __pci_driver = {
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.ops = &northbridge_operations,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x7180,
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};
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static void i440lx_domain_set_resources(device_t dev)
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{
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device_t mc_dev;
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uint32_t pci_tolm;
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pci_tolm = find_pci_tolm(dev->link_list);
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mc_dev = dev->link_list->children;
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if (mc_dev) {
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unsigned long tomk, tolmk;
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int idx;
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/* Figure out which areas are/should be occupied by RAM. The
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* value of the highest DRB denotes the end of the physical
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* memory (in units of 8MB).
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*/
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tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
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/* Convert to KB. */
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tomk *= (8 * 1024);
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printk(BIOS_DEBUG, "Setting RAM size to %lu MB\n", tomk / 1024);
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/* Compute the top of low memory. */
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tolmk = pci_tolm / 1024;
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if (tolmk >= tomk) {
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/* The PCI hole does not overlap the memory. */
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tolmk = tomk;
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}
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/* Report the memory regions. */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tolmk - 768);
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set_top_of_ram(tomk * 1024);
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}
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = i440lx_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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};
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(dev->link_list);
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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}
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_i440lx_ops = {
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CHIP_NAME("Intel 82443LX (440LX) Northbridge")
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.enable_dev = enable_dev,
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};
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@ -1,26 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 Maciej Pijanka <maciej.pijanka@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
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*/
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#ifndef NORTHBRIDGE_INTEL_440LX_H
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#define NORTHBRIDGE_INTEL_440LX_H
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extern unsigned int i440lx_scan_root_bus(device_t root, unsigned int max);
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#endif /* NORTHBRIDGE_INTEL_440LX_H */
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@ -1,453 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Maciej Pijanka <maciej.pijanka@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
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|
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#include <spd.h>
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#include <delay.h>
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#include <stdlib.h>
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#include "i440lx.h"
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/*-----------------------------------------------------------------------------
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Macros and definitions.
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-----------------------------------------------------------------------------*/
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/* Uncomment this to enable debugging output. */
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/* Debugging macros. */
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#if CONFIG_DEBUG_RAM_SETUP
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#define PRINT_DEBUG(x) printk(BIOS_DEBUG, x)
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#define PRINT_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
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#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x)
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#define PRINT_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
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#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
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#else
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#define PRINT_DEBUG(x)
|
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#define PRINT_DEBUG_HEX8(x)
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#define PRINT_DEBUG_HEX16(x)
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#define PRINT_DEBUG_HEX32(x)
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#define DUMPNORTH()
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#endif
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#define NB PCI_DEV(0, 0, 0)
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/* DRAMXC[7:5] - DRAM extended control register (SMS). */
|
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#define RAM_COMMAND_NORMAL 0x0
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#define RAM_COMMAND_NOP 0x1 // (NOPCE)
|
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#define RAM_COMMAND_PRECHARGE 0x2 // ABPCE
|
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#define RAM_COMMAND_MRS 0x3 // MRSCE
|
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#define RAM_COMMAND_CBR 0x4 // CBRC
|
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// rest are reserved
|
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|
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/* Table format: register, bitmask, value. */
|
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static const long register_values[] = {
|
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// ~0x02 == bit 9
|
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// 0x04 == bit 10
|
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// BASE is 0x8A but we dont want bit 9 or 10 have ENABLED so 0x8C
|
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PACCFG + 1, 0x38, 0x8c,
|
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|
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DBC, 0x00, 0xC3,
|
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|
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DRT, 0x00, 0xFF,
|
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DRT+1, 0x00, 0xFF,
|
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|
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DRAMC, 0x00, 0x00, /* disable refresh for now. */
|
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DRAMT, 0x00, 0x00,
|
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|
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PAM0, 0x00, 0x30, // everything is a mem
|
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PAM1, 0x00, 0x33,
|
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PAM2, 0x00, 0x33,
|
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PAM3, 0x00, 0x33,
|
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PAM4, 0x00, 0x33,
|
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PAM5, 0x00, 0x33,
|
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PAM6, 0x00, 0x33,
|
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|
||||
/* Set the DRBs to zero for now, this will be fixed later. */
|
||||
DRB0, 0x00, 0x00,
|
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DRB1, 0x00, 0x00,
|
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DRB2, 0x00, 0x00,
|
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DRB3, 0x00, 0x00,
|
||||
DRB4, 0x00, 0x00,
|
||||
DRB5, 0x00, 0x00,
|
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DRB6, 0x00, 0x00,
|
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DRB7, 0x00, 0x00,
|
||||
|
||||
/* No memory holes. */
|
||||
FDHC, 0x00, 0x00,
|
||||
};
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
SDRAM configuration functions.
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* Send the specified RAM command to all DIMMs.
|
||||
*
|
||||
* @param command The RAM command to send to the DIMM(s).
|
||||
*/
|
||||
static void do_ram_command(u32 command)
|
||||
{
|
||||
int i, caslatency;
|
||||
u8 dimm_start, dimm_end;
|
||||
u16 reg16;
|
||||
u32 addr, addr_offset;
|
||||
|
||||
/* Configure the RAM command. */
|
||||
reg16 = pci_read_config16(NB, DRAMXC);
|
||||
reg16 &= 0xff1f; /* Clear bits 7-5. */
|
||||
reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */
|
||||
pci_write_config16(NB, DRAMXC, reg16);
|
||||
|
||||
/*
|
||||
* RAM_COMMAND_NORMAL affects only the memory controller and
|
||||
* doesn't need to be "sent" to the DIMMs.
|
||||
*/
|
||||
if (command == RAM_COMMAND_NORMAL)
|
||||
return;
|
||||
|
||||
/* Send the RAM command to each row of memory. */
|
||||
dimm_start = 0;
|
||||
for (i = 0; i < (DIMM_SOCKETS * 2); i++) {
|
||||
addr_offset = 0;
|
||||
caslatency = 3; /* TODO: Dynamically get CAS latency later. */
|
||||
|
||||
/* before translation it is
|
||||
*
|
||||
* M[02:00] Burst Length
|
||||
* M[03:03] Burst Type
|
||||
* M[06:04] Cas Latency
|
||||
* 000 - Reserved
|
||||
* 001 - Reserved
|
||||
* 010 - CAS 2
|
||||
* 011 - CAS 3
|
||||
* 100 - Reserved
|
||||
* 101 - Reserved
|
||||
* 110 - Reserved
|
||||
* 111 - Reserved
|
||||
* M[08:07] Op Mode
|
||||
* Must Be 00b (Defined mode)
|
||||
* M[09:09] Write Burst Mode
|
||||
* 0 - Programmed burst length
|
||||
* 1 - Single location access
|
||||
* M[11:10] Reserved
|
||||
* write 0 to ensure compatibility with....
|
||||
*/
|
||||
|
||||
/* seems constructed value will be right shifted by 3 bit, thus constructed value
|
||||
* must be left shifted by 3
|
||||
* so possible formula is (caslatency <<4)|(burst_type << 1)|(burst length)
|
||||
* then << 3 shift to compensate shift in Memory Controller
|
||||
*/
|
||||
if (command == RAM_COMMAND_MRS) {
|
||||
if (caslatency == 3)
|
||||
addr_offset = 0x1d0;
|
||||
if (caslatency == 2)
|
||||
addr_offset = 0x150;
|
||||
}
|
||||
|
||||
dimm_end = pci_read_config8(NB, DRB + i);
|
||||
|
||||
addr = (dimm_start * 8 * 1024 * 1024) + addr_offset;
|
||||
if (dimm_end > dimm_start) {
|
||||
#if 0
|
||||
PRINT_DEBUG(" Sending RAM command 0x");
|
||||
PRINT_DEBUG_HEX16(reg16);
|
||||
PRINT_DEBUG(" to 0x");
|
||||
PRINT_DEBUG_HEX32(addr);
|
||||
PRINT_DEBUG("\n");
|
||||
#endif
|
||||
|
||||
read32(addr);
|
||||
}
|
||||
|
||||
/* Set the start of the next DIMM. */
|
||||
dimm_start = dimm_end;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
DIMM-independant configuration functions.
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
static void spd_enable_refresh(void)
|
||||
{
|
||||
uint8_t reg;
|
||||
|
||||
reg = pci_read_config8(NB, DRAMC);
|
||||
|
||||
/* this chipset offer only two choices regarding refresh
|
||||
* refresh disabled, or refresh normal
|
||||
*/
|
||||
|
||||
pci_write_config8(NB, DRAMC, reg | 0x01);
|
||||
reg = pci_read_config8(NB, DRAMC);
|
||||
|
||||
PRINT_DEBUG("spd_enable_refresh: dramc = 0x");
|
||||
PRINT_DEBUG_HEX8(reg);
|
||||
PRINT_DEBUG("\n");
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Public interface.
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
static void northbridge_init(void)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = pci_read_config32(NB, APBASE);
|
||||
reg32 &= 0xe8000000U;
|
||||
pci_write_config32(NB, APBASE, reg32);
|
||||
|
||||
#if CONFIG_DEBUG_RAM_SETUP
|
||||
/*
|
||||
* apbase dont get set still, no idea what i have doing wrong yet,
|
||||
* i am almost sure that somehow i set it by mistake once, but can't
|
||||
* repeat that.
|
||||
*/
|
||||
reg32 = pci_read_config32(NB, APBASE);
|
||||
PRINT_DEBUG("APBASE ");
|
||||
PRINT_DEBUG_HEX32(reg32);
|
||||
PRINT_DEBUG("\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* This routine sets RAM controller inside northbridge to known state
|
||||
*
|
||||
*/
|
||||
static void sdram_set_registers(void)
|
||||
{
|
||||
int i, max;
|
||||
|
||||
/* nice banner with FSB shown? do we have
|
||||
* any standart policy about such things?
|
||||
*/
|
||||
#if 0
|
||||
uint16_t reg16;
|
||||
reg16 = pci_read_config16(NB, PACCFG);
|
||||
printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\n", (reg16 & 0x4000) ? '0' : '6');
|
||||
#endif
|
||||
|
||||
PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
|
||||
DUMPNORTH();
|
||||
|
||||
northbridge_init();
|
||||
|
||||
max = ARRAY_SIZE(register_values);
|
||||
|
||||
/* Set registers as specified in the register_values[] array. */
|
||||
for (i = 0; i < max; i += 3) {
|
||||
uint8_t reg,tmp;
|
||||
reg = pci_read_config8(NB, register_values[i]);
|
||||
reg &= register_values[i + 1];
|
||||
reg |= register_values[i + 2] & ~(register_values[i + 1]);
|
||||
pci_write_config8(NB, register_values[i], reg);
|
||||
|
||||
/*
|
||||
* i am not sure if that is needed, but was usefull
|
||||
* for me to confirm what got written
|
||||
*/
|
||||
#if CONFIG_DEBUG_RAM_SETUP
|
||||
PRINT_DEBUG(" Set register 0x");
|
||||
PRINT_DEBUG_HEX8(register_values[i]);
|
||||
PRINT_DEBUG(" to 0x");
|
||||
PRINT_DEBUG_HEX8(reg);
|
||||
tmp = pci_read_config8(NB, register_values[i]);
|
||||
PRINT_DEBUG(" readed 0x");
|
||||
PRINT_DEBUG_HEX8(tmp);
|
||||
if (tmp == reg) {
|
||||
PRINT_DEBUG(" OK ");
|
||||
} else {
|
||||
PRINT_DEBUG(" FAIL ");
|
||||
}
|
||||
PRINT_DEBUG("\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
PRINT_DEBUG("Northbridge atexit sdram set registers\n");
|
||||
DUMPNORTH();
|
||||
}
|
||||
|
||||
|
||||
static void sdram_set_spd_registers(void)
|
||||
{
|
||||
int i;
|
||||
u16 memsize = 0;
|
||||
|
||||
for (i = 0; i < DIMM_SOCKETS; i++) {
|
||||
uint16_t ds = 0; // dimm size
|
||||
int j;
|
||||
/* this code skips second bank on each socket (no idea how to fix it now)
|
||||
*/
|
||||
|
||||
PRINT_DEBUG("DIMM");
|
||||
PRINT_DEBUG_HEX8(i);
|
||||
PRINT_DEBUG(" rows: ");
|
||||
PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & 0xFF);
|
||||
PRINT_DEBUG(" rowsize: ");
|
||||
PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE) & 0xFF);
|
||||
PRINT_DEBUG(" modulesize: ");
|
||||
|
||||
j = spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS);
|
||||
if (j < 0)
|
||||
j = 0;
|
||||
else
|
||||
ds = j;
|
||||
|
||||
j = spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
|
||||
|
||||
if (j < 0)
|
||||
j = 0;
|
||||
else
|
||||
ds = ds * (j >> 1); // convert from 4MB to 8MB units in place
|
||||
|
||||
|
||||
/* This is more or less crude hack
|
||||
* allowing to run this target under qemu (even if that is not really
|
||||
* same hardware emulated),
|
||||
* probably some kconfig expert option should be added to enable/disable
|
||||
* this nicelly
|
||||
*/
|
||||
#if 0
|
||||
if (ds == 0 && memsize == 0)
|
||||
ds = 0x8;
|
||||
#endif
|
||||
|
||||
|
||||
// todo: support for bank with not equal sizes as per jedec standart?
|
||||
|
||||
/*
|
||||
* because density is reported in units of 4Mbyte
|
||||
* and rows in device are just value,
|
||||
* and for setting registers we need value in 8Mbyte units
|
||||
*/
|
||||
|
||||
PRINT_DEBUG_HEX16(ds);
|
||||
PRINT_DEBUG("\n");
|
||||
|
||||
memsize += ds;
|
||||
|
||||
pci_write_config8(NB, DRB + (2*i), memsize);
|
||||
pci_write_config8(NB, DRB + (2*i) + 1, memsize);
|
||||
if (ds > 0) {
|
||||
/* i have no idea why pci_read_config16 not work for
|
||||
* me correctly here
|
||||
*/
|
||||
ds = pci_read_config8(NB, DRT+1);
|
||||
ds <<=8;
|
||||
ds |= pci_read_config8(NB, DRT);
|
||||
|
||||
PRINT_DEBUG("DRT ");
|
||||
PRINT_DEBUG_HEX16(ds);
|
||||
|
||||
ds &= ~(0x01 << (4 * i));
|
||||
|
||||
PRINT_DEBUG(" ");
|
||||
PRINT_DEBUG_HEX16(ds);
|
||||
PRINT_DEBUG("\n");
|
||||
|
||||
/*
|
||||
* modify DRT register if current row isn't empty
|
||||
* code assume its SDRAM plugged (should check if its sdram or EDO,
|
||||
* edo would have 0x00 as constand instead 0x10 for SDRAM
|
||||
* also this code is buggy because ignores second row of each dimm socket
|
||||
*/
|
||||
|
||||
/* and as above write_config16 not work here too)
|
||||
* pci_write_config16(NB, DRT, j);
|
||||
*/
|
||||
|
||||
pci_write_config8(NB, DRT+1, ds >> 8);
|
||||
pci_write_config8(NB, DRT, ds & 0xFF);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
PRINT_DEBUG("Mem: 0x");
|
||||
PRINT_DEBUG_HEX16(memsize * 8);
|
||||
PRINT_DEBUG(" MB\n");
|
||||
|
||||
if (memsize == 0) {
|
||||
/* maybe we should use some nice die/hlt sequence with printing on console
|
||||
* that no memory found, get lost, i can't run?
|
||||
* maybe such event_handler can be commonly defined routine to decrease
|
||||
* code duplication?
|
||||
*/
|
||||
PRINT_DEBUG("No memory detected via SPD\n");
|
||||
PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set DRAMC. Don't enable refresh for now. */
|
||||
pci_write_config8(NB, DRAMC, 0x00);
|
||||
|
||||
/* Cas latency 3, and other shouldbe properly from spd too */
|
||||
pci_write_config8(NB, DRAMT, 0xAC);
|
||||
|
||||
/* TODO? */
|
||||
pci_write_config8(NB, PCI_LATENCY_TIMER, 0x40);
|
||||
|
||||
// set drive strength
|
||||
pci_write_config32(NB, MBSC, 0x00000000);
|
||||
}
|
||||
|
||||
static void sdram_enable(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* 0. Wait until power/voltages and clocks are stable (200us). */
|
||||
udelay(200);
|
||||
|
||||
/* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 MHz). */
|
||||
PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
|
||||
do_ram_command(RAM_COMMAND_NOP);
|
||||
udelay(200);
|
||||
|
||||
/* 2. Precharge all. Wait tRP. */
|
||||
PRINT_DEBUG("RAM Enable 2: Precharge all\n");
|
||||
do_ram_command(RAM_COMMAND_PRECHARGE);
|
||||
udelay(1);
|
||||
|
||||
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
|
||||
PRINT_DEBUG("RAM Enable 3: CBR\n");
|
||||
for (i = 0; i < 8; i++) {
|
||||
do_ram_command(RAM_COMMAND_CBR);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* 4. Mode register set. Wait two memory cycles. */
|
||||
PRINT_DEBUG("RAM Enable 4: Mode register set\n");
|
||||
do_ram_command(RAM_COMMAND_MRS);
|
||||
udelay(2);
|
||||
|
||||
/* 5. Normal operation. */
|
||||
PRINT_DEBUG("RAM Enable 5: Normal operation\n");
|
||||
do_ram_command(RAM_COMMAND_NORMAL);
|
||||
udelay(1);
|
||||
|
||||
/* 6. Finally enable refresh. */
|
||||
PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
|
||||
pci_write_config8(NB, DRAMC, 0x01);
|
||||
spd_enable_refresh();
|
||||
udelay(1);
|
||||
|
||||
PRINT_DEBUG("Northbridge following SDRAM init:\n");
|
||||
}
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2009 Maciej Pijanka <maciej.pijanka@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
/* The 440LX supports up to four (single- or double-sided) DIMMs. */
|
||||
#define DIMM_SOCKETS 4
|
||||
|
||||
#endif /* RAMINIT_H */
|
||||
Loading…
Reference in New Issue