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mainboard/google/kahlee: Update chromeos.fmd 

- Remove SI_ALL section.  This is no longer needed as the PSP dirctory
is placed into the RO coreboot section.
- Add 1MB Legacy section.
- Add Memory cache section. These sections are called "MRC", which is
an Intel term, but AMD platforms will use the same regions for saving
the same sort of data.

BUG=b:65497959, b:67035984
TEST=Build & boot kahlee

Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Martin Roth 2017-11-22 19:06:38 -07:00
parent 73031bcce0
commit 320b41b148
1 changed files with 20 additions and 19 deletions
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39
src/mainboard/google/kahlee/chromeos.fmd
View File

@ -1,37 +1,38 @@
FLASH@0xff800000 0x800000 { FLASH@0xFF800000 0x800000 {
SI_ALL@0x0 0xCB000 { SI_BIOS@0x0 0x800000 {
UNUSED@0x00000 0x20000 RW_SECTION_A@0x0 0x21E000 {
AMD_FW@0x20000 0xAB000
}
SI_BIOS@0xCB000 0x735000 {
RW_SECTION_A@0x0 0x21e000 {
VBLOCK_A@0x0 0x10000 VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x20DFC0 FW_MAIN_A(CBFS)@0x10000 0x20DFC0
RW_FWID_A@0x21dfc0 0x40 RW_FWID_A@0x21DFC0 0x40
} }
RW_SECTION_B@0x21e000 0x21e000 { RW_SECTION_B@0x21E000 0x21E000 {
VBLOCK_B@0x0 0x10000 VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x20DFC0 FW_MAIN_B(CBFS)@0x10000 0x20DFC0
RW_FWID_B@0x21dfc0 0x40 RW_FWID_B@0x21DFC0 0x40
} }
RW_MRC_CACHE@0x43C000 0x10000 UNIFIED_MRC_CACHE@0x43C000 0x21000 {
RW_ELOG@0x44C000 0x4000 RECOVERY_MRC_CACHE@0x0 0x10000
RW_SHARED@0x450000 0x4000 { RW_MRC_CACHE@0x10000 0x10000
RW_VAR_MRC_CACHE@0x20000 0x1000
}
RW_ELOG@0x45D000 0x4000
RW_SHARED@0x461000 0x4000 {
SHARED_DATA@0x0 0x2000 SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000 VBLOCK_DEV@0x2000 0x2000
} }
RW_VPD@0x454000 0x2000 RW_VPD@0x465000 0x2000
RW_UNUSED@0x456000 0x3F000 RW_LEGACY@0x467000 0x100000
# RW_LEGACY(CBFS)@0x200000 0x200000 RW_UNUSED@0x567000 0x8000
WP_RO@0x495000 0x2A0000{ WP_RO@0x56F000 0x291000 {
RO_VPD@0x0 0x4000 RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000 RO_UNUSED@0x4000 0xc000
RO_SECTION@0x10000 0x290000 { RO_SECTION@0x10000 0x281000 {
FMAP@0x0 0x800 FMAP@0x0 0x800
RO_FRID@0x800 0x40 RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0 RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0x70000 GBB@0x1000 0x70000
COREBOOT(CBFS)@0x80000 0x210000 COREBOOT(CBFS)@0x71000 0x210000
} }
} }
} }