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soc/intel/apollolake: Fix spacing around operators and commas 

Fix the following errors detected by checkpatch.pl:

ERROR: spaces required around that '==' (ctx:VxO)
ERROR: space required before that '-' (ctx:OxV)
ERROR: spaces required around that '=' (ctx:VxW)
ERROR: spaces required around that '=' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: need consistent spacing around '+' (ctx:VxW)
ERROR: space prohibited before that '++' (ctx:WxB)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space required after that ',' (ctx:VxV)

TEST=Build for reef

Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18720
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2017-03-09 09:42:48 -08:00 committed by Martin Roth
parent 68571c144e
commit 320b7ca44b
5 changed files with 13 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/apollolake/bootblock/bootblock.c
View File

@ -89,7 +89,7 @@ static void cache_bios_region(void)
mtrr = get_free_var_mtrr(); mtrr = get_free_var_mtrr();
if (mtrr==-1) if (mtrr == -1)
return; return;
/* Only the IFD BIOS region is memory mapped (at top of 4G) */ /* Only the IFD BIOS region is memory mapped (at top of 4G) */

7
src/soc/intel/apollolake/gpio.c
View File

@ -52,7 +52,8 @@ static const struct pad_community {
.port = GPIO_N, .port = GPIO_N,
.first_pad = N_OFFSET, .first_pad = N_OFFSET,
.num_gpi_regs = NUM_N_GPI_REGS, .num_gpi_regs = NUM_N_GPI_REGS,
.gpi_offset = NUM_NW_GPI_REGS+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS, .gpi_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
+ NUM_SW_GPI_REGS,
.grp_name = "GPIO_GPE_N", .grp_name = "GPIO_GPE_N",
} }
}; };
@ -144,7 +145,7 @@ static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin)
en_reg = GPI_SMI_EN_OFFSET(group); en_reg = GPI_SMI_EN_OFFSET(group);
value = iosf_read(port, en_reg ); value = iosf_read(port, en_reg );
value |= 1 << (pin % GPIO_MAX_NUM_PER_GROUP); value |= 1 << (pin % GPIO_MAX_NUM_PER_GROUP);
iosf_write(port, en_reg , value); iosf_write(port, en_reg, value);
} }
void gpio_configure_pad(const struct pad_config *cfg) void gpio_configure_pad(const struct pad_config *cfg)
@ -291,7 +292,7 @@ static void print_gpi_status(const struct gpi_status *sts)
abs_bit = bit_set; abs_bit = bit_set;
abs_bit += group * GPIO_MAX_NUM_PER_GROUP; abs_bit += group * GPIO_MAX_NUM_PER_GROUP;
printk(BIOS_DEBUG, "%s %d\n",comm->grp_name, printk(BIOS_DEBUG, "%s %d\n", comm->grp_name,
abs_bit); abs_bit);
} }
} }

6
src/soc/intel/apollolake/graphics.c
View File

@ -97,7 +97,7 @@ static const unsigned short pci_device_ids[] = {
}; };
static const struct pci_driver integrated_graphics_driver __pci_driver = { static const struct pci_driver integrated_graphics_driver __pci_driver = {
.ops = &igd_ops, .ops = &igd_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VENDOR_ID_INTEL,
.devices= pci_device_ids, .devices = pci_device_ids,
}; };

2
src/soc/intel/apollolake/northbridge.c
View File

@ -76,7 +76,7 @@ static int mc_add_imr_resources(device_t dev, int index)
mchbar = (void *)(ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB)); mchbar = (void *)(ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB));
for (i = 0; i < MCH_NUM_IMRS; i ++) { for (i = 0; i < MCH_NUM_IMRS; i++) {
imr_offset = i * MCH_IMR_PITCH; imr_offset = i * MCH_IMR_PITCH;
base = read32(mchbar + imr_offset + MCHBAR_IMR0BASE); base = read32(mchbar + imr_offset + MCHBAR_IMR0BASE);
mask = read32(mchbar + imr_offset + MCHBAR_IMR0MASK); mask = read32(mchbar + imr_offset + MCHBAR_IMR0MASK);

8
src/soc/intel/apollolake/pmutil.c
View File

@ -72,8 +72,8 @@ static uint32_t print_smi_status(uint32_t smi_sts)
[APM_SMI_STS] = "APM", [APM_SMI_STS] = "APM",
[SWSMI_TMR_SMI_STS] = "SWSMI_TMR", [SWSMI_TMR_SMI_STS] = "SWSMI_TMR",
[FAKE_PM1_SMI_STS] = "PM1", [FAKE_PM1_SMI_STS] = "PM1",
[GPIO_SMI_STS]= "GPIO_SMI", [GPIO_SMI_STS] = "GPIO_SMI",
[GPIO_UNLOCK_SMI_STS]= "GPIO_UNLOCK_SSMI", [GPIO_UNLOCK_SMI_STS] = "GPIO_UNLOCK_SSMI",
[MC_SMI_STS] = "MCSMI", [MC_SMI_STS] = "MCSMI",
[TCO_SMI_STS] = "TCO", [TCO_SMI_STS] = "TCO",
[PERIODIC_SMI_STS] = "PERIODIC", [PERIODIC_SMI_STS] = "PERIODIC",
@ -407,7 +407,7 @@ int fill_power_state(struct chipset_power_state *ps)
ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS);
ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); ps->prsts = read32((void *)(pmc_bar0 + PRSTS));
ps->gen_pmcon1 =read32((void *)(pmc_bar0 + GEN_PMCON1)); ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));
ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));
@ -422,7 +422,7 @@ int fill_power_state(struct chipset_power_state *ps)
ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n", printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n",
inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS)); inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS));
for (i=0; i < GPE0_REG_MAX; i++) { for (i = 0; i < GPE0_REG_MAX; i++) {
ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i)); ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i));
ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i)); ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i));
printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",