soc/intel/cannonlake: Add SPI flash controller driver
Add SPI driver code for the SPI flash controller, including both fast_spi and generic_spi. Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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201fa8ffe5
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321111774c
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@ -11,6 +11,8 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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select C_ENVIRONMENT_BOOTBLOCK
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select HAVE_HARD_RESET
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@ -29,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_CSE
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_GPIO
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select SOC_INTEL_COMMON_BLOCK_GSPI
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select SOC_INTEL_COMMON_BLOCK_LPSS
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_RTC
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@ -38,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_TIMER
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
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select SOC_INTEL_COMMON_RESET
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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@ -78,6 +82,11 @@ config CPU_BCLK_MHZ
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int
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default 100
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config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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int
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default 3
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# Clock divider parameters for 115200 baud rate
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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@ -11,20 +11,27 @@ bootblock-y += bootblock/cpu.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += gpio.c
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bootblock-y += gspi.c
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bootblock-y += memmap.c
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bootblock-y += spi.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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romstage-y += gspi.c
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romstage-y += memmap.c
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romstage-y += reset.c
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romstage-y += spi.c
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romstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += chip.c
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ramstage-y += gspi.c
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ramstage-y += memmap.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += spi.c
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ramstage-y += systemagent.c
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ramstage-$(CONFIG_UART_DEBUG) += uart.c
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postcar-y += memmap.c
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postcar-y += spi.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
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@ -18,9 +18,12 @@
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#ifndef _SOC_CHIP_H_
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#define _SOC_CHIP_H_
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#include <intelblocks/gspi.h>
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#include <stdint.h>
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struct soc_intel_cannonlake_config {
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/* GSPI */
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struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
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};
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typedef struct soc_intel_cannonlake_config config_t;
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@ -0,0 +1,71 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <device/device.h>
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#include <intelblocks/gspi.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include "chip.h"
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const struct gspi_cfg *gspi_get_soc_cfg(void)
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{
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DEVTREE_CONST struct soc_intel_cannonlake_config *config;
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int devfn = SA_DEVFN_ROOT;
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DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
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__func__);
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return NULL;
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}
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config = dev->chip_info;
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return &config->gspi[0];
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}
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uintptr_t gspi_get_soc_early_base(void)
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{
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return EARLY_GSPI_BASE_ADDRESS;
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}
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/*
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* SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
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* the bus # accordingly when referring to SPI / GSPI bus numbers.
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*/
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#define GSPI_TO_SPI_BUS(x) ((x) + 1)
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#define SPI_TO_GSPI_BUS(x) ((x) - 1)
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int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
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{
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if (spi_bus == 0)
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return -1;
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*gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
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if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
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return -1;
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return 0;
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}
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int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
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{
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if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
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return -1;
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return spi_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
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}
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@ -173,6 +173,7 @@ static inline int spi_devfn_to_bus(unsigned int devfn)
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case PCH_DEVFN_SPI: return 0;
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case PCH_DEVFN_GSPI0: return 1;
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case PCH_DEVFN_GSPI1: return 2;
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case PCH_DEVFN_GSPI2: return 3;
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}
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return -1;
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}
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@ -183,6 +184,7 @@ static inline int spi_bus_to_devfn(unsigned int bus)
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case 0: return PCH_DEVFN_SPI;
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case 1: return PCH_DEVFN_GSPI0;
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case 2: return PCH_DEVFN_GSPI1;
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case 3: return PCH_DEVFN_GSPI2;
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}
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return -1;
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}
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@ -0,0 +1,71 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <device/spi.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/gspi.h>
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#include <soc/ramstage.h>
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#include <soc/pci_devs.h>
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#include <spi-generic.h>
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const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
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{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
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#if !ENV_SMM
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{ .ctrlr = &gspi_ctrlr, .bus_start = 1,
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.bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
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#endif
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};
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const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
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#if ENV_RAMSTAGE
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static int spi_dev_to_bus(struct device *dev)
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{
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return spi_devfn_to_bus(dev->path.pci.devfn);
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}
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static struct spi_bus_operations spi_bus_ops = {
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.dev_to_bus = &spi_dev_to_bus,
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};
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static struct device_operations spi_dev_ops = {
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.read_resources = &pci_dev_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.scan_bus = &scan_generic_bus,
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.ops_spi_bus = &spi_bus_ops,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI,
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PCI_DEVICE_ID_INTEL_CNL_SPI0,
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PCI_DEVICE_ID_INTEL_CNL_SPI1,
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PCI_DEVICE_ID_INTEL_CNL_SPI2,
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0
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};
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static const struct pci_driver pch_spi __pci_driver = {
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.ops = &spi_dev_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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#endif
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