Various cosmetic changes and coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
0f86732a5e
commit
322076cdad
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@ -1,7 +1,7 @@
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##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2007 AMD
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## Copyright (C) 2007 AMD
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## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
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## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
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## (Thanks to LSRA University of Mannheim for their support)
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@ -26,47 +26,46 @@
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FAILOVER_IMAGE
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default ROM_SECTION_SIZE = FAILOVER_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
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default ROM_SECTION_SIZE = FAILOVER_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
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else
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
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else
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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## Compute the start location and size size of the LinuxBIOS bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_PAYLOAD_START = ( 0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1 )
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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## Compute where this copy of LinuxBIOS will start in the boot ROM.
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## Compute a range of ROM that can be cached to speed up LinuxBIOS
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2. (here 64 Kbyte)
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## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte)
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE = ( 64 * 1024 )
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default XIP_ROM_SIZE = (64 * 1024)
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if USE_FAILOVER_IMAGE
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default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
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default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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else
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if USE_FALLBACK_IMAGE
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default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE )
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else
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default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
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end
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if USE_FALLBACK_IMAGE
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default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
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else
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default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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end
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end
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arch i386 end
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@ -107,51 +106,48 @@ if USE_DCACHE_RAM
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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## Build our 16 bit and 32 bit LinuxBIOS entry code.
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##
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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## Build our reset vector (this is where LinuxBIOS is entered).
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##
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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if USE_DCACHE_RAM
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@ -161,7 +157,7 @@ else
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end
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##
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## Include an id string (For safe flashing)
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## Include an ID string (for safe flashing).
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##
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mainboardinit southbridge/nvidia/ck804/id.inc
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ldscript /southbridge/nvidia/ck804/id.lds
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@ -190,22 +186,22 @@ end
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###
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### This is the early phase of linuxBIOS startup
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### This is the early phase of LinuxBIOS startup.
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover_failover.lds
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end
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end
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if USE_FAILOVER_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover_failover.lds
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end
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end
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else
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if USE_FALLBACK_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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end
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end
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if USE_FALLBACK_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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end
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end
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end
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###
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@ -230,124 +226,123 @@ if CONFIG_CHIP_NAME
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config chip.h
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end
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_939
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device apic 0 on end
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end
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end
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chip northbridge/amd/amdk8/root_complex # Root complex
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device apic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_939 # Socket 939 CPU
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 # mc0
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device pci 18.0 on # northbridge
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# Devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/ck804
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/ite/it8712f
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x03f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x03f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off # Com2
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io 0x60 = 0x02f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel Port
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io 0x60 = 0x0378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # Environment Controller
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io 0x60 = 0x0290
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io 0x62 = 0x0000
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irq 0x70 = 0x00
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x0060
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io 0x62 = 0x0064
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irq 0x70 = 0x01
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irq 0x71 = 0x02
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end
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device pnp 2e.6 on # Mouse
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irq 0x70 = 0x0c
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irq 0x71 = 0x02
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end
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device pnp 2e.7 on # GPIO config
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# Set GPIO 1 & 2
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io 0x25 = 0x0000
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# Set GPIO 3 & 4
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io 0x27 = 0x2540
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# GPIO Polarity for Set 3
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io 0xb2 = 0x2100
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# GPIO Pin Internal Pull up for Set 3
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io 0xba = 0x0100
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# Simple I/O register config
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io 0xc0 = 0x0000
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io 0xc2 = 0x2540
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io 0xc8 = 0x0000
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io 0xca = 0x0500
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end
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device pnp 2e.8 off end # Midi port
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device pnp 2e.9 off end # Game port
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device pnp 2e.a off end # IR
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end
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end
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device pci 1.1 on # SM 0
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# chip drivers/generic/generic #dimm 0-0-0
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic #dimm 0-0-1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-0
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-0
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-1
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# device i2c 55 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-0
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# device i2c 56 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-1
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# device i2c 57 on end
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# end
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end # SM
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 off end # ACI
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device pci 4.1 off end # MCI
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device pci 6.0 on end # IDE
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device pci 7.0 on end # SATA 1
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device pci 8.0 on end # SATA 0
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device pci 9.0 on end # PCI
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device pci a.0 on end # NIC
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device pci b.0 on end # PCI E 3
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device pci c.0 on end # PCI E 2
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device pci d.0 on end # PCI E 1
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device pci e.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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# register "mac_eeprom_smbus" = "3"
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# register "mac_eeprom_addr" = "0x51"
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end
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end # device pci 18.0
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end # mc0
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end # pci_domain
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end # root_complex
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8 # mc0
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device pci 18.0 on # Northbridge
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# Devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/ck804 # Southbridge
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/ite/it8712f # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # Environment controller
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io 0x60 = 0x290
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io 0x62 = 0x0000
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irq 0x70 = 0x00
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end
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device pnp 2e.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x71 = 2
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end
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device pnp 2e.6 on # PS/2 mouse
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irq 0x70 = 12
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irq 0x71 = 2
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end
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device pnp 2e.7 on # GPIO config
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# Set GPIO 1 & 2
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io 0x25 = 0x0000
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# Set GPIO 3 & 4
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io 0x27 = 0x2540
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# GPIO Polarity for Set 3
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io 0xb2 = 0x2100
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# GPIO Pin Internal Pull up for Set 3
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io 0xba = 0x0100
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# Simple I/O register config
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io 0xc0 = 0x0000
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io 0xc2 = 0x2540
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io 0xc8 = 0x0000
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io 0xca = 0x0500
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end
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device pnp 2e.8 off end # Midi port
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device pnp 2e.9 off end # Game port
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device pnp 2e.a off end # IR
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end
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end
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device pci 1.1 on # SM 0
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# chip drivers/generic/generic #dimm 0-0-0
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic #dimm 0-0-1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-0
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-0
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-1
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# device i2c 55 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-0
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# device i2c 56 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-1
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# device i2c 57 on end
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# end
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end
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 off end # Onboard audio (ACI)
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device pci 4.1 off end # Onboard modem (MCI)
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device pci 6.0 on end # IDE
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device pci 7.0 on end # SATA 1
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device pci 8.0 on end # SATA 0
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device pci 9.0 on end # PCI
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device pci a.0 on end # NIC
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device pci b.0 on end # PCI E 3
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device pci c.0 on end # PCI E 2
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device pci d.0 on end # PCI E 1
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device pci e.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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# register "mac_eeprom_smbus" = "3"
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# register "mac_eeprom_addr" = "0x51"
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end
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end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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end
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end
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