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mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rpl 

Configure GPIO pins, add Kconfig options and enable
TPM device in devicetree.

Add H1 TPM IRQ GPIO pin in gpio.c

BUG=none
BRANCH=firmware-brya-14505.B
Cq-Depend: chromium:3774914
TEST=Boot the image and check the successful TPM
communication in verstage,romstage & ramstage from
coreboot logs.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I1b4119373f69954d620dc09e637a7571312a5fc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This commit is contained in:
Bora Guvendik 2022-07-19 13:50:41 -07:00 committed by Felix Held
parent 8754965db1
commit 323bddb1bd
4 changed files with 43 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/intel/adlrvp/Kconfig
View File

@ -40,6 +40,9 @@ config BOARD_INTEL_ADLRVP_RPL_EXT_EC
select SOC_INTEL_ALDERLAKE_PCH_P
select GEN3_EXTERNAL_CLOCK_BUFFER
select DRIVERS_WWAN_FM350GL
select MAINBOARD_HAS_TPM2
select SPI_TPM
select TPM_GOOGLE_CR50
config BOARD_INTEL_ADLRVP_P_MCHP
select BOARD_INTEL_ADLRVP_COMMON
@ -167,7 +170,7 @@ endchoice
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC
select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC
select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC
select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC
@ -176,14 +179,14 @@ config UART_FOR_CONSOLE
default 0
config DRIVER_TPM_SPI_BUS
default 0x2 if BOARD_INTEL_ADLRVP_M_EXT_EC
default 0x2 if BOARD_INTEL_ADLRVP_RPL_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC
config USE_PM_ACPI_TIMER
default n if BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_N
config TPM_TIS_ACPI_INTERRUPT
int
default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3)
default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3)
config GEN3_EXTERNAL_CLOCK_BUFFER
bool

25
src/mainboard/intel/adlrvp/devicetree.cb
View File

@ -1,5 +1,14 @@
chip soc/intel/alderlake
# This disables autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses.
register "gpio_override_pm" = "1"
register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_1]" = "0"
register "gpio_pm[COMM_2]" = "0"
register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
@ -137,14 +146,14 @@ chip soc/intel/alderlake
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
}"
register "serial_io_gspi_cs_mode" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
[PchSerialIoIndexGSPI1] = 1,
[PchSerialIoIndexGSPI2] = 0,
[PchSerialIoIndexGSPI3] = 0,
}"
@ -172,6 +181,10 @@ chip soc/intel/alderlake
# Intel Common SoC Config
register "common_soc_config" = "{
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
@ -429,6 +442,14 @@ chip soc/intel/alderlake
device ref uart0 on end
device ref gspi0 on end
device ref p2sb on end
device ref gspi1 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
device spi 0 on end
end
end
device ref hda on
chip drivers/intel/soundwire
device generic 0 on

12
src/mainboard/intel/adlrvp/early_gpio.c
View File

@ -118,6 +118,18 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
/*_TPM_*/
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
/* F16 : GSPI1_CS0N */
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
/* F11 : GSPI1_CLK */
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
/* F13 : GSPI1_MISO */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
/* F12 : GSPI1_MOSI */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
};
static const struct pad_config early_uart_gpio_table[] = {

4
src/mainboard/intel/adlrvp/gpio.c
View File

@ -45,8 +45,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
/* EC_SLP_S0_CS_N */
PAD_CFG_GPO(GPP_F9, 1, PLTRST),
/* WIFI RF KILL */
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
/* DISP_AUX_N_BIAS_GPIO */
PAD_CFG_GPO(GPP_E23, 1, PLTRST),
/* WWAN WAKE N*/
@ -264,6 +262,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
/* A22 : HDMI CRLS CTRLDATA */
PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT)
};
void variant_configure_gpio_pads(void)