diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index c0442c479a..c56d271af9 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -182,6 +182,7 @@ The boards in this section are not real mainboards, but emulators.
 
 - [LabTop Mk IV](starlabs/labtop_cml.md)
 - [StarLite Mk III](starlabs/lite_glk.md)
+- [StarLite Mk IV](starlabs/lite_glkr.md)
 - [StarBook Mk V](starlabs/starbook_tgl.md)
 
 ## Supermicro
diff --git a/Documentation/mainboard/starlabs/lite_glkr.md b/Documentation/mainboard/starlabs/lite_glkr.md
new file mode 100644
index 0000000000..52e3898cf1
--- /dev/null
+++ b/Documentation/mainboard/starlabs/lite_glkr.md
@@ -0,0 +1,82 @@
+# StarLite Mk III
+
+## Specs
+- CPU (full processor specs available at https://ark.intel.com)
+    - Intel N5030 (Gemini Lake Refresh)
+- EC
+    - Nuvoton NPCE985P/G
+    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
+    - Battery
+    - Charger, using AC adapter or USB-C PD
+    - Suspend / resume
+- GPU
+    - Intel UHD Graphics 605
+    - GOP driver is recommended, VBT is provided
+    - eDP 11.6-inch 1920x1080 LCD
+    - HDMI video
+    - USB-C DisplayPort video
+- Memory
+    - 8GB on-board
+- Networking
+    - 9461 CNVi WiFi / Bluetooth soldered to PCBA
+- Sound
+    - Realtek ALC269
+    - Internal speakers
+    - Internal microphone
+    - Combined headphone / microphone 3.5-mm jack
+    - HDMI audio
+    - USB-C DisplayPort audio
+- Storage
+    - M.2 SATA SSD
+    - RTS5129 MicroSD card reader
+- USB
+    - 1200x1600 CCD camera
+    - USB 3.1 Gen 1 Type-C (left)
+    - USB 3.1 Gen 1 Type-A (left)
+    - USB 3.1 Gen 1 Type-A (right)
+
+## Building coreboot
+
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* IFWI Image (ifwi.rom)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr
+make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Gigadevice |
++---------------------+------------+
+| Model               | GD25LQ64(B)|
++---------------------+------------+
+| Size                | 8 MiB      |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig
index de2e8e17ba..ced67d9e43 100644
--- a/src/mainboard/starlabs/lite/Kconfig
+++ b/src/mainboard/starlabs/lite/Kconfig
@@ -2,7 +2,6 @@ config BOARD_STARLABS_LITE_SERIES
 	def_bool n
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_I2C_HID
-	select EC_STARLABS_ITE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
@@ -20,6 +19,13 @@ config BOARD_STARLABS_LITE_SERIES
 
 config BOARD_STARLABS_LITE_GLK
 	select BOARD_STARLABS_LITE_SERIES
+	select EC_STARLABS_ITE
+	select EC_STARLABS_KBL_LEVELS
+	select SOC_INTEL_GEMINILAKE
+
+config BOARD_STARLABS_LITE_GLKR
+	select BOARD_STARLABS_LITE_SERIES
+	select EC_STARLABS_NUVOTON
 	select EC_STARLABS_KBL_LEVELS
 	select SOC_INTEL_GEMINILAKE
 
@@ -32,7 +38,8 @@ config EC_GPE_SCI
 	default 0x26
 
 config EC_VARIANT_DIR
-	default "glk"
+	default "glk"  if BOARD_STARLABS_LITE_GLK
+	default "glkr" if BOARD_STARLABS_LITE_GLKR
 
 config FMDFILE
 	default "src/mainboard/starlabs/lite/board.fmd"
@@ -42,10 +49,12 @@ config MAINBOARD_DIR
 
 config MAINBOARD_FAMILY
 	string
-	default "I3"
+	default "I3" if BOARD_STARLABS_LITE_GLK
+	default "I4" if BOARD_STARLABS_LITE_GLKR
 
 config MAINBOARD_PART_NUMBER
-	default "Lite Mk III"
+	default "Lite Mk III" if BOARD_STARLABS_LITE_GLK
+	default "Lite Mk IV"  if BOARD_STARLABS_LITE_GLKR
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	string
@@ -53,7 +62,8 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
 
 config TRACKPAD_INTERRUPT
 	hex
-	default 0x1
+	default 0x1 if BOARD_STARLABS_LITE_GLK
+	default 0x0 if BOARD_STARLABS_LITE_GLKR
 
 config TIANOCORE_BOOTSPLASH_FILE
 	string
@@ -63,5 +73,6 @@ config UART_FOR_CONSOLE
 	default 2
 
 config VARIANT_DIR
-	default "glk"
+	default "glk"  if BOARD_STARLABS_LITE_GLK
+	default "glkr" if BOARD_STARLABS_LITE_GLKR
 endif
diff --git a/src/mainboard/starlabs/lite/Kconfig.name b/src/mainboard/starlabs/lite/Kconfig.name
index 7cfb61291d..1046c976a3 100644
--- a/src/mainboard/starlabs/lite/Kconfig.name
+++ b/src/mainboard/starlabs/lite/Kconfig.name
@@ -2,3 +2,6 @@ comment "Star Labs Lite Series"
 
 config BOARD_STARLABS_LITE_GLK
 	bool "Star Labs Lite Mk III (N5000)"
+
+config BOARD_STARLABS_LITE_GLKR
+	bool "Star Labs Lite Mk IV (N5030)"
diff --git a/src/mainboard/starlabs/lite/variants/glk/gpio.c b/src/mainboard/starlabs/lite/variants/glk/gpio.c
index 0bda6ea58c..9d83554cdd 100644
--- a/src/mainboard/starlabs/lite/variants/glk/gpio.c
+++ b/src/mainboard/starlabs/lite/variants/glk/gpio.c
@@ -480,7 +480,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPIO_183, DN_20K),
 	/* GPIO_184:	Not Connected		*/
 	PAD_NC(GPIO_184, DN_20K),
-	/* GPIO_187:	WLAN_RST_N_R		*/
+	/* GPIO_185:	WLAN_RST_N_R		*/
 	_PAD_CFG_STRUCT(GPIO_185, PAD_FUNC(GPIO) | PAD_RESET(DEEP) |
 		PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
 	/* GPIO_186:	Not Connected		*/
diff --git a/src/mainboard/starlabs/lite/variants/glkr/Makefile.inc b/src/mainboard/starlabs/lite/variants/glkr/Makefile.inc
new file mode 100644
index 0000000000..ae3ec84c1d
--- /dev/null
+++ b/src/mainboard/starlabs/lite/variants/glkr/Makefile.inc
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
+
+romstage-y += romstage.c
diff --git a/src/mainboard/starlabs/lite/variants/glkr/data.vbt b/src/mainboard/starlabs/lite/variants/glkr/data.vbt
new file mode 100644
index 0000000000..2c016f4fa4
Binary files /dev/null and b/src/mainboard/starlabs/lite/variants/glkr/data.vbt differ
diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
new file mode 100644
index 0000000000..895c194cdd
--- /dev/null
+++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
@@ -0,0 +1,153 @@
+chip soc/intel/apollolake
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# Graphics
+	# TODO:
+	# register "panel_cfg" = "{
+	#	.up_delay_ms			=  0,				// T3
+	#	.backlight_on_delay_ms		=  0,				// T7
+	#	.backlight_off_delay_ms		=  0,				// T9
+	#	.down_delay_ms			=  0,				// T10
+	#	.cycle_delay_ms			=  500,				// T12
+	#	.backlight_pwm_hz		=  200,				// PWM
+	# }"
+
+# PM Util (soc/intel/apollolake/pmutil.c)
+	# Enable the correct decode ranges on the LPC bus.
+	register "lpc_ioe"                      = "LPC_IOE_EC_4E_4F |
+						   LPC_IOE_EC_62_66 |
+						   LPC_IOE_KBC_60_64"
+
+	# Enable Audio Clock and Power gating
+	register "hdaudio_clk_gate_enable"	= "1"
+	register "hdaudio_pwr_gate_enable"	= "1"
+	register "hdaudio_bios_config_lockdown"	= "1"
+
+	register "pnp_settings"			= "PNP_PERF_POWER"
+
+	register "ModPhyIfValue"		= "0x12"
+
+	register "usb_config_override"		= "1"
+	register "DisableComplianceMode"	= "1"
+
+	register "pcie_rp_clkreq_pin[0]"	= "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]"	= "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]"	= "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]"	= "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]"	= "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]"	= "CLKREQ_DISABLED"
+
+	register "pcie_rp_deemphasis_enable[0]"	= "1"
+	register "pcie_rp_deemphasis_enable[1]"	= "1"
+	register "pcie_rp_deemphasis_enable[2]"	= "1"
+	register "pcie_rp_deemphasis_enable[3]"	= "1"
+	register "pcie_rp_deemphasis_enable[4]"	= "1"
+	register "pcie_rp_deemphasis_enable[5]"	= "1"
+
+	# GPE configuration
+	register "gpe0_dw1"			= "PMC_GPE_NW_63_32"
+	register "gpe0_dw2"			= "PMC_GPE_N_95_64"
+	register "gpe0_dw3"			= "PMC_GPE_NW_31_0"
+
+	register "slp_s3_assertion_width_usecs"	= "50000"
+
+	device domain 0 on
+		device pci 00.0 on  end						# Host Bridge
+		device pci 00.1 on  end						# DPTF
+		device pci 00.2 off end						# NPK
+		device pci 02.0 on  end						# Gen
+		device pci 03.0 off end						# Iunit
+		device pci 0c.0 on						# CNVi
+			chip drivers/wifi/generic
+				register "wake" = "GPE0A_CNVI_PME_STS"
+				device generic 0 on end
+			end
+		end
+		device pci 0d.0 off end						# P2SB
+		device pci 0d.1 hidden end					# PMC
+		device pci 0d.2 on  end						# SPI
+		device pci 0d.3 off end						# Shared SRAM
+		device pci 0e.0 on						# Audio
+			subsystemid 0x10ec 0x111e
+		end
+		device pci 0f.0 on  end						# Heci1
+		device pci 0f.1 on  end						# Heci2
+		device pci 0f.2 on  end						# Heci3
+		device pci 11.0 off end						# ISH
+		device pci 12.0 on  end						# SATA
+		device pci 13.0 off end						# PCIe-A 0 Slot 1
+		device pci 13.1 off end						# PCIe-A 1
+		device pci 13.2 off end						# PCIe-A 2 Onboard Lan
+		device pci 13.3 off end						# PCIe-A 3
+		device pci 14.0 off end						# PCIe-B 0 Slot2
+		device pci 14.1 off end						# PCIe-B 1 Onboard M2 Slot(Wifi/BT)
+		device pci 15.0 on						# XHCI
+			### USB 2.0 Devices
+			# Motherboard USB Type C
+			register "usb2_port[0]"		= "PORT_EN(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb2_port[1]"		= "PORT_EN(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb2_port[3]"		= "PORT_EN(OC_SKIP)"
+			# Daughterboard SD Card
+			register "usb2_port[5]"		= "PORT_EN(OC_SKIP)"
+			# Internal Webcam
+			register "usb2_port[7]"		= "PORT_EN(OC_SKIP)"
+
+			### USB 3.0 Devices
+			# Motherboard USB 3.0
+			register "usb3_port[0]"		= "PORT_EN(OC_SKIP)"
+			# Motherboard USB Type C
+			register "usb3_port[1]"		= "PORT_EN(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb3_port[3]"		= "PORT_EN(OC_SKIP)"
+		end
+		device pci 15.1 off end						# XDCI
+		device pci 16.0 off end						# I2C0
+		device pci 16.1 off end						# I2C1
+		device pci 16.2 off end						# I2C2
+		device pci 16.3 off end						# I2C3
+		device pci 17.0 on  end						# I2C4
+		device pci 17.1 off end						# I2C5
+		device pci 17.2 off end						# I2C6
+		device pci 17.3 on						# I2C7
+			# Handled by touchpad.asl
+		end
+		device pci 18.0 on  end						# UART #0
+		device pci 18.1 off end						# UART #1
+		device pci 18.2 on  end						# UART #2
+		device pci 18.3 off end						# UART #3
+		device pci 19.0 off end						# SPI #0
+		device pci 19.1 off end						# SPI #1
+		device pci 19.2 on  end						# SPI #2
+		device pci 1a.0 off end						# PWM
+		device pci 1b.0 off end						# SDCard
+		device pci 1c.0 off end						# eMMC
+		device pci 1e.0 off end						# SDIO
+		device pci 1f.0 on						# LPC Interface
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.00 on  end			# IO Interface
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# Mouse
+				device pnp 4e.06 on				# Keyboard
+					io 0x60			= 0x0060
+					io 0x62			= 0x0064
+					irq 0x70		= 1
+				end
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.1d off end			# Extended Shared Memory (ESHM)
+				device pnp 4e.1e off end			# Power Management Channel 4
+			end
+		end
+		device pci 1f.1 off  end					# SMBus
+	end
+	chip drivers/crb
+		device mmio 0xfed40000 on end
+	end
+end
diff --git a/src/mainboard/starlabs/lite/variants/glkr/gpio.c b/src/mainboard/starlabs/lite/variants/glkr/gpio.c
new file mode 100644
index 0000000000..48292adba1
--- /dev/null
+++ b/src/mainboard/starlabs/lite/variants/glkr/gpio.c
@@ -0,0 +1,519 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <string.h>
+#include <variants.h>
+#include <types.h>
+
+/* Early pad configuration in bootblock. */
+const struct pad_config early_gpio_table[] = {
+	/* GPIO_64:	UART2_TXD	*/
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
+	/* GPIO_65:	UART2_RXD	*/
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage. */
+const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group NorthWest ------- */
+	/* GPIO_0:	XDP_H_TCK		*/
+	PAD_NC(GPIO_0, DN_20K),
+	/* GPIO_1:	XDP_H_TRST_N		*/
+	PAD_NC(GPIO_1, DN_20K),
+	/* GPIO_2:	XDP_H_TMS		*/
+	PAD_NC(GPIO_2, DN_20K),
+	/* GPIO_3:	XDP_H_TDI		*/
+	PAD_NC(GPIO_3, DN_20K),
+	/* GPIO_4:	XDP_H_TDO		*/
+	PAD_NC(GPIO_4, DN_20K),
+	/* GPIO_5:	Not Connected		*/
+	PAD_NC(GPIO_5, DN_20K),
+	/* GPIO_6:	XDP_H_PREQ_N		*/
+	PAD_NC(GPIO_6, DN_20K),
+	/* GPIO_7:	XDP_H_PRDY_N		*/
+	PAD_NC(GPIO_7, DN_20K),
+	/* GPIO_8:	Not Connected		*/
+	PAD_NC(GPIO_8, DN_20K),
+	/* GPIO_9:	Not Connected		*/
+	PAD_NC(GPIO_9, DN_20K),
+	/* GPIO_10:	Not Connected		*/
+	PAD_NC(GPIO_10, DN_20K),
+	/* GPIO_11:	Not Connected		*/
+	PAD_NC(GPIO_11, DN_20K),
+	/* GPIO_12:	Not Connected		*/
+	PAD_NC(GPIO_12, DN_20K),
+	/* GPIO_13:	Not Connected		*/
+	PAD_NC(GPIO_13, DN_20K),
+	/* GPIO_14:	Not Connected		*/
+	PAD_NC(GPIO_14, DN_20K),
+	/* GPIO_15:	Not Connected		*/
+	PAD_NC(GPIO_15, DN_20K),
+	/* GPIO_16:	Not Connected		*/
+	PAD_NC(GPIO_16, DN_20K),
+	/* GPIO_17:	Not Connected		*/
+	PAD_NC(GPIO_17, DN_20K),
+	/* GPIO_18:	Not Connected		*/
+	PAD_NC(GPIO_18, DN_20K),
+	/* GPIO_19:	PMIC_IRQ#		*/
+	_PAD_CFG_STRUCT(GPIO_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) |
+		PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) |
+		PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_20:	Not Connected		*/
+	PAD_NC(GPIO_20, DN_20K),
+	/* GPIO_21:	Not Connected		*/
+	PAD_NC(GPIO_21, DN_20K),
+	/* GPIO_22:	Not Connected		*/
+	PAD_NC(GPIO_22, DN_20K),
+	/* GPIO_23:	Not Connected		*/
+	PAD_NC(GPIO_23, DN_20K),
+	/* GPIO_24:	Not Connected		*/
+	PAD_NC(GPIO_24, DN_20K),
+	/* GPIO_25:	Not Connected		*/
+	PAD_NC(GPIO_25, DN_20K),
+	/* GPIO_26:	TCH_INT_N		*/
+	PAD_NC(GPIO_26, DN_20K),
+	/* GPIO_27:	GPIO_27			*/
+	PAD_NC(GPIO_27, DN_20K),
+	/* GPIO_28:	GPIO_28			*/
+	PAD_NC(GPIO_27, DN_20K),
+	/* GPIO_29:	Not Connected		*/
+	PAD_NC(GPIO_29, DN_20K),
+	/* GPIO_30:	SAR_PROX_INT		*/
+	_PAD_CFG_STRUCT(GPIO_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) |
+		PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) |
+		PAD_IOSSTATE(IGNORE)),
+	/* GPIO_31:	ACCEL1_INT		*/
+	PAD_NC(GPIO_31, DN_20K),
+	/* GPIO_32:	SAR_PROX_RST		*/
+	PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_32, DN_20K, DEEP, OFF, IGNORE, ENPD, ACPI),
+	/* GPIO_33:	Not Connected		*/
+	PAD_NC(GPIO_33, DN_20K),
+	/* GPIO_34:	Not Connected		*/
+	PAD_NC(GPIO_34, DN_20K),
+	/* GPIO_35:	Not Connected		*/
+	PAD_NC(GPIO_35, DN_20K),
+	/* GPIO_36:	Not Connected		*/
+	PAD_NC(GPIO_36, DN_20K),
+	/* GPIO_37:	Not Connected		*/
+	PAD_NC(GPIO_37, DN_20K),
+	/* GPIO_38:	WAKE_SCI#		*/
+	_PAD_CFG_STRUCT(GPIO_38, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) |
+		PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_39:	FP_RST#			*/
+	PAD_NC(GPIO_39, DN_20K),
+	/* GPIO_40:	Not Connected		*/
+	PAD_NC(GPIO_40, DN_20K),
+	/* GPIO_41:	Not Connected		*/
+	PAD_NC(GPIO_41, DN_20K),
+	/* GPIO_42:	SECURITY_FLASH		*/
+	_PAD_CFG_STRUCT(GPIO_42, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)),
+	/* GPIO_43:	GPIO_43			*/
+	_PAD_CFG_STRUCT(GPIO_43, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)),
+	/* GPIO_44:	GPIO_44			*/
+	_PAD_CFG_STRUCT(GPIO_44, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSTERM(ENPU)),
+	/* GPIO_45:	GPIO_45			*/
+	_PAD_CFG_STRUCT(GPIO_45, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSTERM(ENPU)),
+	/* GPIO_46:	Not Connected		*/
+	PAD_NC(GPIO_46, DN_20K),
+	/* GPIO_47:	Not Connected		*/
+	PAD_NC(GPIO_47, DN_20K),
+	/* GPIO_48:	OZ8283_I2C_SDA		*/
+	_PAD_CFG_STRUCT(GPIO_48, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_49:	OZ8283_I2C_SCL		*/
+	_PAD_CFG_STRUCT(GPIO_49, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_50:	ISH_I2C0_SDA		*/
+	_PAD_CFG_STRUCT(GPIO_50, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)),
+	/* GPIO_51:	ISH_I2C0_SCL		*/
+	_PAD_CFG_STRUCT(GPIO_51, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)),
+	/* GPIO_52:	I2C1_SDA		*/
+	_PAD_CFG_STRUCT(GPIO_52, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_53:	I2C1_SCL		*/
+	_PAD_CFG_STRUCT(GPIO_53, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_54:	Not Connected		*/
+	PAD_NC(GPIO_54, DN_20K),
+	/* GPIO_55:	Not Connected		*/
+	PAD_NC(GPIO_55, DN_20K),
+	/* GPIO_56:	Not Connected		*/
+	PAD_NC(GPIO_56, DN_20K),
+	/* GPIO_57:	Not Connected		*/
+	PAD_NC(GPIO_57, DN_20K),
+	/* GPIO_57:	TOUCH_I2C_SDA		*/
+	PAD_NC(GPIO_58, DN_20K),
+	/* GPIO_57:	TOUCH_I2C_CLK		*/
+	PAD_NC(GPIO_59, DN_20K),
+	_PAD_CFG_STRUCT(GPIO_60, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_61, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPIO_62, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_63, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_66:	UART2_RTS		*/
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxLASTRxE, ENPU),
+	/* GPIO_67:	EC_SMI_N		*/
+	_PAD_CFG_STRUCT(GPIO_67, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) |
+		(1 << 1), PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)),
+	_PAD_CFG_STRUCT(GPIO_68, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_69, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_70, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_71, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_72, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 1, DEEP, UP_20K, IGNORE, ENPU),
+	_PAD_CFG_STRUCT(GPIO_74, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(UP_20K)
+		| PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
+	_PAD_CFG_STRUCT(GPIO_75, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	/* GPIO_211 - RESERVED */
+	/* GPIO_212:	Not Connected		*/
+	 PAD_NC(GPIO_212, DN_20K),
+	/* GPIO_213:	Not Connected		*/
+	PAD_NC(GPIO_213, DN_20K),
+	/* GPIO_214:	Not Connected		*/
+	PAD_NC(GPIO_214, DN_20K),
+
+	/* ------- GPIO Group North ------- */
+	/* GPIO_76:	VCCIN_VIDALERT_N	*/
+	_PAD_CFG_STRUCT(GPIO_76, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_77:	VCCIN_VIDSOUT		*/
+	_PAD_CFG_STRUCT(GPIO_77, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_78:	VCCIN_VIDSCK		*/
+	_PAD_CFG_STRUCT(GPIO_78, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_79:	FP_SSP0_CLK		*/
+	_PAD_CFG_STRUCT(GPIO_79, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD)),
+	/* GPIO_80:	FP_SSP0_FS0		*/
+	_PAD_CFG_STRUCT(GPIO_80, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD)),
+	/* GPIO_81:	GPIO_81			*/
+	_PAD_CFG_STRUCT(GPIO_81, PAD_FUNC(NF3) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF) | (1 << 1), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)),
+	/* GPIO_82:	FP_SSP0_MISO		*/
+	_PAD_CFG_STRUCT(GPIO_82, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD)),
+	/* GPIO_83:	GPIO_83			*/
+	_PAD_CFG_STRUCT(GPIO_83, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD)),
+
+	PAD_CFG_GPI_TRIG_OWN(GPIO_84, DN_20K, DEEP, OFF, ACPI),
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_85, 1, DEEP, UP_20K, IGNORE, ENPU),
+	_PAD_CFG_STRUCT(GPIO_86, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)),
+	_PAD_CFG_STRUCT(GPIO_87, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_88, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_89, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_90, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)),
+	_PAD_CFG_STRUCT(GPIO_91, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_92, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_DISABLE), PAD_PULL(NATIVE)),
+	_PAD_CFG_STRUCT(GPIO_93, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)),
+	_PAD_CFG_STRUCT(GPIO_94, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)),
+	_PAD_CFG_STRUCT(GPIO_95, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)),
+	_PAD_CFG_STRUCT(GPIO_96, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_DISABLE), PAD_PULL(NATIVE)),
+	/* GPIO_97:	GPIO_97			*/
+	_PAD_CFG_STRUCT(GPIO_97, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_DISABLE), PAD_PULL(NATIVE)),
+	/* GPIO_98:	PMU_PLTRST_N		*/
+	_PAD_CFG_STRUCT(GPIO_98, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_99:	SOC_PMU_PWRBTN_N	*/
+	_PAD_CFG_STRUCT(GPIO_99, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_100:	SLP_S0#			*/
+	_PAD_CFG_STRUCT(GPIO_100, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
+		PAD_IOSSTATE(IGNORE)),
+	/* GPIO_101:	SLP_S3#			*/
+	_PAD_CFG_STRUCT(GPIO_101, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
+		PAD_IOSSTATE(IGNORE)),
+	/* GPIO_102:	SLP_S4#			*/
+	_PAD_CFG_STRUCT(GPIO_102, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
+		PAD_IOSSTATE(IGNORE)),
+	/* GPIO_103:	SUSPWRDNACK		*/
+	_PAD_CFG_STRUCT(GPIO_103, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
+		PAD_IOSSTATE(IGNORE)),
+	/* GPIO_104:	Not Connected		*/
+	PAD_NC(GPIO_104, DN_20K),
+	/* GPIO_105:	GPIO_105		*/
+	_PAD_CFG_STRUCT(GPIO_105, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_106:	PMU_BATLOW_N		*/
+	_PAD_CFG_STRUCT(GPIO_106, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_107:	PMU_RSTBTN#		*/
+	_PAD_CFG_STRUCT(GPIO_107, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_108:	SUS_CLK			*/
+	_PAD_CFG_STRUCT(GPIO_108, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
+		PAD_IOSSTATE(IGNORE)),
+	/* GPIO_109:	PMU_SUS_STAT#		*/
+	_PAD_CFG_STRUCT(GPIO_109, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
+		PAD_IOSSTATE(IGNORE)),
+	/* GPIO_110:	Not Connected		*/
+	PAD_NC(GPIO_110, DN_20K),
+	/* GPIO_111:	Not Connected		*/
+	PAD_NC(GPIO_111, DN_20K),
+	/* GPIO_112:	Not Connected		*/
+	PAD_NC(GPIO_112, DN_20K),
+	/* GPIO_113:	Not Connected		*/
+	PAD_NC(GPIO_113, DN_20K),
+	/* GPIO_114:	I2C_SDA_CPU		*/
+	_PAD_CFG_STRUCT(GPIO_114, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)),
+	/* GPIO_115:	I2C_SDL_CPU		*/
+	_PAD_CFG_STRUCT(GPIO_115, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)),
+	/* GPIO_116:	WLAN_PCIE_WAKE#		*/
+	_PAD_CFG_STRUCT(GPIO_116, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_117:	WLAN_PCIE_WAKE#1	*/
+	PAD_NC(GPIO_117, DN_20K),
+	/* GPIO_118:	Not Connected		*/
+	PAD_NC(GPIO_118, DN_20K),
+	/* GPIO_119:	Not Connected		*/
+	PAD_NC(GPIO_119, DN_20K),
+	/* GPIO_120:	WLAN_CLK_REQ#		*/
+	_PAD_CFG_STRUCT(GPIO_120, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)),
+	/* GPIO_121:	WLAN_CLK_REQ#		*/
+	_PAD_CFG_STRUCT(GPIO_121, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)),
+	/* GPIO_122:	Not Connected		*/
+	PAD_NC(GPIO_122, DN_20K),
+	/* GPIO_123:	Not Connected		*/
+	PAD_NC(GPIO_123, DN_20K),
+	/* GPIO_124:	DDI0_DDC_SDA		*/
+	_PAD_CFG_STRUCT(GPIO_124, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPU)),
+	/* GPIO_125:	DDI0_DDC_SCL		*/
+	_PAD_CFG_STRUCT(GPIO_125, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPU)),
+	/* GPIO_126:	Not Connected		*/
+	PAD_NC(GPIO_126, DN_20K),
+	/* GPIO_127:	Not Connected		*/
+	PAD_NC(GPIO_127, DN_20K),
+	/* GPIO_128:	EDP_VDD_EN		*/
+	_PAD_CFG_STRUCT(GPIO_128, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
+		PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPD)),
+	/* GPIO_129:	EDP_BKLT_EN		*/
+	_PAD_CFG_STRUCT(GPIO_129, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
+		PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPD)),
+	/* GPIO_130:	EDP_BKLT_PWM		*/
+	_PAD_CFG_STRUCT(GPIO_130, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
+		PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPD)),
+	/* GPIO_131:	DDI0_HPD_N		*/
+	_PAD_CFG_STRUCT(GPIO_131, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_132:	DDI0_HPD_SOC		*/
+	_PAD_CFG_STRUCT(GPIO_132, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_133:	EDP_HPD_LS		*/
+	_PAD_CFG_STRUCT(GPIO_133, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPU)),
+	/* GPIO_134:	Touch_Panel_RST#	*/
+	PAD_NC(GPIO_134, DN_20K),
+	/* GPIO_15:	MIPI_RST		*/
+	PAD_CFG_GPI_TRIG_OWN(GPIO_135, DN_20K, DEEP, OFF, ACPI),
+	/* GPIO_136:	Not Connected		*/
+	PAD_NC(GPIO_136, DN_20K),
+	/* GPIO_137:	Not Connected		*/
+	PAD_NC(GPIO_137, DN_20K),
+	/* GPIO_138:	GPIO_138		*/
+	_PAD_CFG_STRUCT(GPIO_138, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	/* GPIO_139:	Not Connected		*/
+	PAD_NC(GPIO_139, DN_20K),
+	/* GPIO_140:	SATA_DEVSLP_C		*/
+	PAD_CFG_GPI_TRIG_OWN(GPIO_140, DN_20K, DEEP, OFF, ACPI),
+	/* GPIO_141:	Not Connected		*/
+	PAD_NC(GPIO_141, DN_20K),
+	/* GPIO_142:	PMU_WAKE#		*/
+	_PAD_CFG_STRUCT(GPIO_142, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) |
+		(1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)),
+	/* GPIO_143:	Not Connected		*/
+	PAD_NC(GPIO_143, DN_20K),
+	_PAD_CFG_STRUCT(GPIO_144, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_145, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_146, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_147, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSTERM(ENPU)),
+	_PAD_CFG_STRUCT(GPIO_148, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(HIZCRx1)),
+	_PAD_CFG_STRUCT(GPIO_149, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(HIZCRx1)),
+	_PAD_CFG_STRUCT(GPIO_150, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) |
+		PAD_IOSTERM(ENPU)),
+	_PAD_CFG_STRUCT(GPIO_151, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) |
+		PAD_IOSTERM(ENPU)),
+	_PAD_CFG_STRUCT(GPIO_152, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) |
+		PAD_IOSTERM(ENPU)), _PAD_CFG_STRUCT(GPIO_153, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) |
+		PAD_IOSTERM(ENPU)), _PAD_CFG_STRUCT(GPIO_154, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPIO_155, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) |
+		PAD_IOSTERM(ENPU)),
+
+	/* ----- GPIO Group Audio ----- */
+	/* GPIO_156:	FP_INT#			*/
+	PAD_NC(GPIO_156, DN_20K),
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, ENPU),
+	_PAD_CFG_STRUCT(GPIO_158, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	PAD_CFG_GPI_TRIG_OWN(GPIO_159, DN_20K, DEEP, OFF, ACPI),
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 1, DEEP, UP_20K, TxLASTRxE, ENPU),
+	PAD_CFG_GPI_TRIG_OWN(GPIO_161, DN_20K, DEEP, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPIO_162, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_163, 1, DEEP, UP_20K, IGNORE, ENPU),
+	/* GPIO_164:	GPIO_164		*/
+	PAD_CFG_GPI_TRIG_OWN(GPIO_164, DN_20K, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPIO_165, DN_20K, DEEP, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPIO_166, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),
+	_PAD_CFG_STRUCT(GPIO_167, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),
+	_PAD_CFG_STRUCT(GPIO_168, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_IOSSTATE(HIZCRx1)),
+	_PAD_CFG_STRUCT(GPIO_169, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),
+	_PAD_CFG_STRUCT(GPIO_170, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),
+	_PAD_CFG_STRUCT(GPIO_171, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	PAD_CFG_GPI_TRIG_OWN(GPIO_172, DN_20K, DEEP, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPIO_173, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_174, 1, DEEP, UP_20K, TxLASTRxE, ENPU),
+	PAD_CFG_GPI_TRIG_OWN(GPIO_175, DN_20K, DEEP, OFF, ACPI),
+
+	/* ----- GPIO Group SCC ----- */
+	/* GPIO_176:	TP_INT#			*/
+	PAD_CFG_GPI_GPIO_DRIVER(GPIO_176, NONE, PLTRST),
+	/* GPIO_177:	SMB_SOC_CLK		*/
+	_PAD_CFG_STRUCT(GPIO_177, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_178:	Not Connected		*/
+	PAD_NC(GPIO_178, DN_20K),
+	/* GPIO_197:	Not Connected		*/
+	PAD_NC(GPIO_197, DN_20K),
+	/* GPIO_179:	Not Connected		*/
+	PAD_NC(GPIO_179, DN_20K),
+	/* GPIO_181:	Not Connected		*/
+	PAD_NC(GPIO_181, DN_20K),
+	/* GPIO_182:	Not Connected		*/
+	PAD_NC(GPIO_182, DN_20K),
+	/* GPIO_183:	Not Connected		*/
+	PAD_NC(GPIO_183, DN_20K),
+	/* GPIO_184:	Not Connected		*/
+	PAD_NC(GPIO_184, DN_20K),
+	/* GPIO_185:	Not Connected		*/
+	PAD_NC(GPIO_185, DN_20K),
+	/* GPIO_186:	Not Connected		*/
+	PAD_NC(GPIO_186, DN_20K),
+	/* GPIO_187:	Not Connected		*/
+	PAD_NC(GPIO_187, DN_20K),
+	/* GPIO_188:	SDMMC3_PWR_EN_N		*/
+	_PAD_CFG_STRUCT(GPIO_188, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_210:	GPIO_210		*/
+	_PAD_CFG_STRUCT(GPIO_210, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)),
+	/* GPIO_189:	Not Connected		*/
+	PAD_NC(GPIO_189, DN_20K),
+	/* GPIO_190:	Not Connected		*/
+	PAD_NC(GPIO_190, DN_20K),
+
+	_PAD_CFG_STRUCT(GPIO_191, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_192, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) |
+		PAD_IOSTERM(ENPU)),
+	_PAD_CFG_STRUCT(GPIO_193, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_194, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) |
+		PAD_IOSTERM(ENPU)),
+	/* GPIO_195:	CNVI_RF_RESET_N		*/
+	_PAD_CFG_STRUCT(GPIO_195, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)),
+
+	_PAD_CFG_STRUCT(GPIO_196, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
+		PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)),
+	_PAD_CFG_STRUCT(GPIO_197, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
+		PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K) | PAD_IOSTERM(ENPD)),
+	/* GPIO_198:	EMMC_CLK		*/
+	PAD_NC(GPIO_198, DN_20K),
+	/* GPIO_200:	EMMC_DATA_0		*/
+	PAD_NC(GPIO_200, DN_20K),
+	/* GPIO_201:	EMMC_DATA_1		*/
+	PAD_NC(GPIO_201, DN_20K),
+	/* GPIO_202:	EMMC_DATA_2		*/
+	PAD_NC(GPIO_202, DN_20K),
+	/* GPIO_203:	EMMC_DATA_3		*/
+	PAD_NC(GPIO_203, DN_20K),
+	/* GPIO_204:	EMMC_DATA_4		*/
+	PAD_NC(GPIO_204, DN_20K),
+	/* GPIO_205:	EMMC_DATA_5		*/
+	PAD_NC(GPIO_205, DN_20K),
+	/* GPIO_206:	EMMC_DATA_6		*/
+	PAD_NC(GPIO_206, DN_20K),
+	/* GPIO_207:	EMMC_DATA_7		*/
+	PAD_NC(GPIO_207, DN_20K),
+	/* GPIO_208:	EMMC_CMD		*/
+	PAD_NC(GPIO_208, DN_20K),
+	/* GPIO_209:	EMMC_STROBE		*/
+	PAD_NC(GPIO_209, DN_20K),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
diff --git a/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c b/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c
new file mode 100644
index 0000000000..f873afa622
--- /dev/null
+++ b/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
+	0x10ec111e,	/* Subsystem ID */
+	15,		/* Number of jacks (NID entries) */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID */
+	AZALIA_SUBVENDOR(0, 0x1C6C1240),
+
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x94171110),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04ab1020),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x93171110),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x042b1010),
+
+	0x00370600,
+	0x00270600,
+	0x00b707C0,
+	0x00d70740,
+
+	0x0017a200,
+	0x0017c621,
+	0x0017a208,
+	0x00170500,
+
+	0x8086280d,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/starlabs/lite/variants/glkr/romstage.c b/src/mainboard/starlabs/lite/variants/glkr/romstage.c
new file mode 100644
index 0000000000..ea0d1c0c39
--- /dev/null
+++ b/src/mainboard/starlabs/lite/variants/glkr/romstage.c
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+static const struct lpddr4_sku skus[] = {
+	[0] = {
+		.speed			= LP4_SPEED_2133,
+		.ch0_rank_density	= LP4_16Gb_DENSITY,
+		.ch1_rank_density	= LP4_16Gb_DENSITY,
+		.ch0_dual_rank		= 0,
+		.ch1_dual_rank		= 0,
+		.part_num		= "D9SKJ",
+	},
+};
+
+static const struct lpddr4_cfg lp4cfg = {
+	.skus = skus,
+	.num_skus = ARRAY_SIZE(skus),
+};
+
+static const uint8_t ch0_bit_swizzling[] = {
+	0x03, 0x01, 0x04, 0x02, 0x00, 0x05, 0x07, 0x06,
+	0x08, 0x0a, 0x0b, 0x09, 0x0c, 0x0d, 0x0f, 0x0e,
+	0x17, 0x13, 0x11, 0x10, 0x15, 0x14, 0x16, 0x12,
+	0x1d, 0x1c, 0x1f, 0x19, 0x1e, 0x18, 0x1b, 0x1a
+};
+
+static const uint8_t ch1_bit_swizzling[] = {
+	0x00, 0x06, 0x07, 0x05, 0x03, 0x02, 0x01, 0x04,
+	0x0c, 0x0f, 0x0d, 0x08, 0x09, 0x0a, 0x0b, 0x0e,
+	0x15, 0x11, 0x13, 0x17, 0x12, 0x19, 0x14, 0x16,
+	0x18, 0x1c, 0x19, 0x1a, 0x1b, 0x1d, 0x1f, 0x1e
+};
+
+static const uint8_t ch2_bit_swizzling[] = {
+	0x05, 0x04, 0x02, 0x03, 0x07, 0x01, 0x00, 0x06,
+	0x09, 0x0d, 0x0a, 0x0c, 0x0f, 0x0b, 0x0e, 0x08,
+	0x17, 0x10, 0x13, 0x11, 0x15, 0x14, 0x12, 0x16,
+	0x1c, 0x1a, 0x1e, 0x1b, 0x1d, 0x1f, 0x19, 0x18
+};
+
+static const uint8_t ch3_bit_swizzling[] = {
+	0x00, 0x04, 0x05, 0x06, 0x01, 0x03, 0x02, 0x07,
+	0x08, 0x0f, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x09,
+	0x12, 0x16, 0x13, 0x11, 0x14, 0x17, 0x15, 0x19,
+	0x1d, 0x1e, 0x18, 0x1b, 0x1c, 0x1a, 0x19, 0x1f
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *config = &memupd->FspmConfig;
+
+	config->Package					= 0x01,
+	config->Profile					= 0x06,
+	config->MemoryDown				= 0x01,
+	config->DDR3LPageSize				= 0x01,
+	config->DDR3LASR				= 0x00,
+	config->ScramblerSupport			= 0x01,
+	config->ChannelHashMask				= 0x36,
+	config->SliceHashMask				= 0x09,
+	config->InterleavedMode				= 0x02,
+	config->ChannelsSlicesEnable			= 0x00,
+	config->MinRefRate2xEnable			= 0x00,
+	config->DualRankSupportEnable			= 0x00,
+	config->RmtMode					= 0x00,
+	config->MemorySizeLimit				= 0x00,
+	config->LowMemoryMaxValue			= 0x00,
+	config->DisableFastBoot				= 0x00,
+	config->HighMemoryMaxValue			= 0x00,
+	config->DIMM0SPDAddress				= 0x00,
+	config->DIMM1SPDAddress				= 0x00,
+
+	config->Ch0_RankEnable				= 0x03,
+	config->Ch0_DeviceWidth				= 0x01,
+	config->Ch0_DramDensity				= 0x04,
+	config->Ch0_Option				= 0x03,
+	config->Ch0_OdtConfig				= 0x00,
+	config->Ch0_TristateClk1			= 0x00,
+	config->Ch0_Mode2N				= 0x00,
+	config->Ch0_OdtLevels				= 0x00,
+
+	config->Ch1_RankEnable				= 0x03,
+	config->Ch1_DeviceWidth				= 0x01,
+	config->Ch1_DramDensity				= 0x04,
+	config->Ch1_Option				= 0x03,
+	config->Ch1_OdtConfig				= 0x00,
+	config->Ch1_TristateClk1			= 0x00,
+	config->Ch1_Mode2N				= 0x00,
+	config->Ch1_OdtLevels				= 0x00,
+
+	config->Ch2_RankEnable				= 0x00,
+	config->Ch2_DeviceWidth				= 0x00,
+	config->Ch2_DramDensity				= 0x00,
+	config->Ch2_Option				= 0x00,
+	config->Ch2_OdtConfig				= 0x00,
+	config->Ch2_TristateClk1			= 0x00,
+	config->Ch2_Mode2N				= 0x00,
+	config->Ch2_OdtLevels				= 0x00,
+
+	config->Ch3_RankEnable				= 0x00,
+	config->Ch3_DeviceWidth				= 0x00,
+	config->Ch3_DramDensity				= 0x00,
+	config->Ch3_Option				= 0x00,
+	config->Ch3_OdtConfig				= 0x00,
+	config->Ch3_TristateClk1			= 0x00,
+	config->Ch3_Mode2N				= 0x00,
+	config->Ch3_OdtLevels				= 0x00,
+
+	config->RmtCheckRun				= 0x00,
+	config->RmtMarginCheckScaleHighThreshold	= 0x00,
+	config->MsgLevelMask				= 0x00,
+
+	memcpy(config->Ch0_Bit_swizzling, &ch0_bit_swizzling,
+			sizeof(ch0_bit_swizzling));
+	memcpy(config->Ch1_Bit_swizzling, &ch1_bit_swizzling,
+			sizeof(ch1_bit_swizzling));
+	memcpy(config->Ch2_Bit_swizzling, &ch2_bit_swizzling,
+			sizeof(ch2_bit_swizzling));
+	memcpy(config->Ch3_Bit_swizzling, &ch3_bit_swizzling,
+			sizeof(ch3_bit_swizzling));
+}
+
+void mainboard_save_dimm_info(void)
+{
+	save_lpddr4_dimm_info(&lp4cfg, 0);
+}