soc/intel/skylake: Add tsc_freq.c to verstage

This is required to provide tsc freq required by timer library.

BUG=b:35583330
TEST=Verified that delay(5) in verstage adds a delay of 5 seconds.

Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19094
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/soc/intel/skylake/Makefile.inc

@@ -33,6 +33,7 @@ verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
 verstage-y += pmutil.c
 verstage-y += bootblock/i2c.c
 verstage-y += spi.c
+verstage-y += tsc_freq.c
 
 romstage-y += flash_controller.c
 romstage-y += gpio.c