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drivers/genesyslogic/gl9755: Disable ASPM L0s support 

When the entry delay of L0s is less than the entry delay of L1, GL9755
will enter L0s state first. When it exits from L0s state, the time of L1
entry will be reset. Therefore, the conditions for entering L1 state
cannot be met. In order to enter L1 state, L0s needs to be disabled.

BUG=b:195611000
TEST=Verify GL9755 enters L1 by observing CLKREQ# de-asserts.

Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: If121b5cb534eb32bac8992683c3f0eee8946acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Ben Chuang 2021-09-14 11:31:42 +08:00 committed by Tim Wawrzynczak
parent 333652c5b2
commit 325f431a91
2 changed files with 4 additions and 0 deletions
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3
src/drivers/genesyslogic/gl9755/gl9755.c
View File

@ -28,6 +28,9 @@ static void gl9755_enable(struct device *dev)
reg |= CFG2_LAT_L1_64US;
pci_write_config32(dev, CFG2, reg);
/* Disable ASPM L0s support */
pci_and_config32(dev, CFG2, ~CFG2_L0S_SUPPORT);
/* Turn off debug mode to enable SCP/OCP */
pci_and_config32(dev, CFG3, ~SCP_DEBUG);

1
src/drivers/genesyslogic/gl9755/gl9755.h
View File

@ -10,6 +10,7 @@
#define CFG2 0x48
#define CFG2_LAT_L1_MASK ((0x7 << 12) | (0x7 << 3))
#define CFG2_LAT_L1_64US ((0x6 << 12) | (0x6 << 3))
#define CFG2_L0S_SUPPORT (0x1 << 6)
#define LTR 0x5C
#define SNOOP_VALUE 0x25
#define SNOOP_SCALE (0x3 << 10)