mb/google/octopus/variants/dood: Disable XHCI LFPS power management

LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.

Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:155955302
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] are set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>

src/mainboard/google/octopus/variants/dood/overridetree.cb

@@ -149,4 +149,5 @@ chip soc/intel/apollolake
 
 	# Disable compliance mode
 	register "DisableComplianceMode" = "1"
+	register "disable_xhci_lfps_pm" = "0"
 end

src/mainboard/google/octopus/variants/dood/variant.c

@@ -8,6 +8,7 @@
 #include <delay.h>
 #include <gpio.h>
 #include <ec/google/chromeec/ec.h>
+#include <soc/intel/apollolake/chip.h>
 
 enum {
 	SKU_1_LTE  = 1, /* Wifi + LTE */
@@ -61,3 +62,21 @@ void variant_smi_sleep(u8 slp_typ)
 		return;
 	}
 }
+
+void variant_update_devtree(struct device *dev)
+{
+	struct soc_intel_apollolake_config *cfg = NULL;
+
+	cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
+
+	if (cfg != NULL && cfg->disable_xhci_lfps_pm) {
+		switch (google_chromeec_get_board_sku()) {
+		case SKU_1_LTE:
+		case SKU_3_LTE_2CAM:
+			cfg->disable_xhci_lfps_pm = 1;
+			return;
+		default:
+			return;
+		}
+	}
+}