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mb/lenovo/t410: Update PCH PCIe RP comments 

Looks like the comments were derived from a preproduction board's
schematics. Production boards use a different port mapping.

Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Angel Pons 2021-06-03 18:41:24 +02:00 committed by Nico Huber
parent 54f86a5a07
commit 3269ad328a
1 changed files with 9 additions and 9 deletions
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16
src/mainboard/lenovo/t410/devicetree.cb
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@ -71,11 +71,11 @@ chip northbridge/intel/ironlake
subsystemid 0x17aa 0x215e
end
device pci 1c.0 on end # PCIe Port #1 (wlan)
device pci 1c.1 off end # PCIe Port #2 (wwan)
device pci 1c.2 off end # PCIe Port #3 (wusb)
device pci 1c.3 on end # PCIe Port #4 (ExpressCard)
device pci 1c.4 on
device pci 1c.0 on end # PCIe Port #1: WWAN mPCIe slot
device pci 1c.1 off end # PCIe Port #2: WLAN mPCIe slot
device pci 1c.2 off end # PCIe Port #3: WUSB mPCIe slot
device pci 1c.3 on end # PCIe Port #4: ExpressCard
device pci 1c.4 on # PCIe Port #5: Ricoh SD & FireWire
subsystemid 0x17aa 0x2133
chip drivers/ricoh/rce822
register "sdwppol" = "1"
@ -84,10 +84,10 @@ chip northbridge/intel/ironlake
subsystemid 0x17aa 0x2134
end
end
end # PCIe Port #5 (Ricoh SD & FW)
device pci 1c.5 off end # PCIe Port #6
end
device pci 1c.5 off end # PCIe Port #6: Intel GbE PHY (not PCIe)
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8 Intel Gigabit Ethernet PHY (not PCIe)
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on # USB2 EHCI
subsystemid 0x17aa 0x2163