sb/intel/spi: read FLCOMP descriptor early and cache it
Change-Id: I4e5fe3ff083f2d0db1cfde16550b57537d5f7262 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/c/28349 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -121,6 +121,7 @@ typedef struct ich9_spi_regs {
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typedef struct ich_spi_controller {
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int locked;
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uint32_t flmap0;
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uint32_t flcomp;
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uint32_t hsfs;
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ich9_spi_regs *ich9_spi;
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@ -346,6 +347,8 @@ void spi_init(void)
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if (cntlr->hsfs & HSFS_FDV) {
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writel_ (4, &ich9_spi->fdoc);
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cntlr->flmap0 = readl_(&ich9_spi->fdod);
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writel_ (0x1000, &ich9_spi->fdoc);
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cntlr->flcomp = readl_(&ich9_spi->fdod);
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}
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}
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@ -930,7 +933,6 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi,
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struct spi_flash *flash)
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{
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ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint32_t flcomp;
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if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX))
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return spi_flash_generic_probe(spi, flash);
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@ -959,15 +961,12 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi,
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break;
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}
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writel_ (0x1000, &cntlr->ich9_spi->fdoc);
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flcomp = readl_(&cntlr->ich9_spi->fdod);
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flash->size = 1 << (19 + (flcomp & 7));
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flash->size = 1 << (19 + (cntlr->flcomp & 7));
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flash->ops = &spi_flash_ops;
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if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3))
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flash->size += 1 << (19 + ((flcomp >> 3) & 7));
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flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7));
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printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
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return 0;
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