nb/intel/haswell: Define and use MMCONF_BUS_NUMBER

Change-Id: I0d6338f763a78895b1ae14d1ab68253851b6c283
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49763
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/haswell/Kconfig

@@ -36,6 +36,10 @@ config VGA_BIOS_ID
 config MMCONF_BASE_ADDRESS
 	default 0xf0000000
 
+config MMCONF_BUS_NUMBER
+	int
+	default 64
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xff7c0000

src/northbridge/intel/haswell/acpi.c

@@ -11,15 +11,8 @@
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-	u32 length, pciexbar;
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-
+			CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
-	if (!decode_pcie_bar(&pciexbar, &length))
-		return current;
-
-	const int max_buses = length / MiB;
-
-	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
-					     max_buses - 1);
 
 	return current;
 }

src/northbridge/intel/haswell/acpi/hostbridge.asl

@@ -179,7 +179,7 @@ Device (PDRC)
 		Memory32Fixed (ReadWrite, DEFAULT_MCHBAR,   0x00008000)
 		Memory32Fixed (ReadWrite, DEFAULT_DMIBAR,   0x00001000)
 		Memory32Fixed (ReadWrite, DEFAULT_EPBAR,    0x00001000)
-		Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
+		Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
 		Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
 		Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
 		Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

src/northbridge/intel/haswell/bootblock.c

@@ -1,25 +1,34 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/bootblock.h>
+#include <assert.h>
 #include <device/pci_ops.h>
+#include <types.h>
 #include "haswell.h"
 
+static uint32_t encode_pciexbar_length(void)
+{
+	switch (CONFIG_MMCONF_BUS_NUMBER) {
+		case 256: return 0 << 1;
+		case 128: return 1 << 1;
+		case  64: return 2 << 1;
+		default:  return dead_code_t(uint32_t);
+	}
+}
+
 void bootblock_early_northbridge_init(void)
 {
-	uint32_t reg;
-
 	/*
-	 * The "io" variant of the config access is explicitly used to setup the PCIEXBAR
+	 * The "io" variant of the config access is explicitly used to setup the
-	 * because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent
+	 * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
-	 * non-explicit config accesses use MCFG. This code also assumes that
+	 * subsequent non-explicit config accesses use MCFG. This code also assumes
-	 * bootblock_northbridge_init() is the first thing called in the non-asm
+	 * that bootblock_northbridge_init() is the first thing called in the non-asm
-	 * boot block code. The final assumption is that no assembly code is using
+	 * boot block code. The final assumption is that no assembly code is using the
-	 * the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
+	 * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
 	 *
 	 * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
 	 */
-	reg = 0;
+	const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg);
+	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
-	reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
 	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
 }

src/northbridge/intel/haswell/haswell.h

@@ -92,8 +92,6 @@ void haswell_unhide_peg(void);
 
 void report_platform_info(void);
 
-int decode_pcie_bar(u32 *const base, u32 *const len);
-
 #include <device/device.h>
 
 struct acpi_rsdp;

src/northbridge/intel/haswell/northbridge.c

@@ -18,46 +18,6 @@
 #include "chip.h"
 #include "haswell.h"
 
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
-{
-	u32 pciexbar_reg, mask;
-
-	*base = 0;
-	*len = 0;
-
-	pciexbar_reg = pci_read_config32(dev, index);
-
-	if (!(pciexbar_reg & (1 << 0)))
-		return 0;
-
-	switch ((pciexbar_reg >> 1) & 3) {
-	case 0: /* 256MB */
-		mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28);
-		*base = pciexbar_reg & mask;
-		*len = 256 * 1024 * 1024;
-		return 1;
-	case 1: /* 128M */
-		mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28);
-		mask |= (1 << 27);
-		*base = pciexbar_reg & mask;
-		*len = 128 * 1024 * 1024;
-		return 1;
-	case 2: /* 64M */
-		mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28);
-		mask |= (1 << 27) | (1 << 26);
-		*base = pciexbar_reg & mask;
-		*len = 64 * 1024 * 1024;
-		return 1;
-	}
-
-	return 0;
-}
-
-int decode_pcie_bar(u32 *const base, u32 *const len)
-{
-	return get_pcie_bar(pcidev_on_root(0, 0), PCIEXBAR, base, len);
-}
-
 static const char *northbridge_acpi_name(const struct device *dev)
 {
 	if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -127,7 +87,6 @@ struct fixed_mmio_descriptor {
 
 #define SIZE_KB(x) ((x) * 1024)
 struct fixed_mmio_descriptor mc_fixed_resources[] = {
-	{ PCIEXBAR, SIZE_KB(0),  get_pcie_bar,      "PCIEXBAR" },
 	{ MCHBAR,   SIZE_KB(32), get_bar,           "MCHBAR"   },
 	{ DMIBAR,   SIZE_KB(4),  get_bar,           "DMIBAR"   },
 	{ EPBAR,    SIZE_KB(4),  get_bar,           "EPBAR"    },
@@ -162,6 +121,8 @@ static void mc_add_fixed_mmio_resources(struct device *dev)
 		       __func__, mc_fixed_resources[i].description, index,
 		       (unsigned long)base, (unsigned long)(base + size - 1));
 	}
+
+	mmconf_resource(dev, PCIEXBAR);
 }
 
 /*