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cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place 

Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2019-02-01 13:07:42 +01:00 committed by Patrick Georgi
parent e951e8ec7f
commit 3286848a7a
2 changed files with 2 additions and 4 deletions
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2
src/include/cpu/x86/msr.h
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@ -37,6 +37,8 @@
#define IA32_PERF_CTL 0x199 #define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b #define IA32_THERM_INTERRUPT 0x19b
#define IA32_MISC_ENABLE 0x1a0 #define IA32_MISC_ENABLE 0x1a0
#define FAST_STRINGS_ENABLE_BIT (1 << 0)
#define SPEED_STEP_ENABLE_BIT (1 << 16)
#define IA32_ENERGY_PERF_BIAS 0x1b0 #define IA32_ENERGY_PERF_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_NORMAL 6

4
src/soc/intel/denverton_ns/include/soc/msr.h
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@ -96,10 +96,6 @@
#define SMRR_SUPPORTED (1 << 11) #define SMRR_SUPPORTED (1 << 11)
#define PRMRR_SUPPORTED (1 << 12) #define PRMRR_SUPPORTED (1 << 12)
/* IA32_MISC_ENABLE bits */
#define FAST_STRINGS_ENABLE_BIT (1 << 0)
#define SPEED_STEP_ENABLE_BIT (1 << 16)
/* Read BCLK from MSR */ /* Read BCLK from MSR */
unsigned int bus_freq_khz(void); unsigned int bus_freq_khz(void);