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AMD CPU and chipset fixes for compilation with gcc 4.6 

Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/266
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
Stefan Reinauer 2011-10-13 17:04:02 -07:00 committed by Uwe Hermann
parent ab87254b61
commit 328a694a3f
5 changed files with 8 additions and 8 deletions
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4
src/northbridge/amd/amdk8/early_ht.c
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@ -16,8 +16,8 @@ static void enumerate_ht_chain(void)
device_t dev;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
//let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid;
uint8_t real_last_pos;
unsigned real_last_unitid = 0;
uint8_t real_last_pos = 0;
int ht_dev_num = 0; // except host_bridge
uint8_t end_used = 0;
#endif

4
src/northbridge/amd/amdk8/incoherent_ht.c
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@ -305,8 +305,8 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
//let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid;
uint8_t real_last_pos;
unsigned real_last_unitid = 0;
uint8_t real_last_pos = 0;
int ht_dev_num = 0;
uint8_t end_used = 0;
#endif

4
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@ -1353,7 +1353,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
u16 tCKproposed16x;
u8 CLactual, CLdesired, CLT_Fail;
u8 smbaddr, byte, bytex;
u8 smbaddr, byte = 0, bytex = 0;
CASLatLow = 0xFF;
CASLatHigh = 0xFF;
@ -2768,7 +2768,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat,
u8 dct, u32 dev, u32 index_reg)
{
u8 Smallest, Largest;
u8 Smallest = 0, Largest = 0;
u32 val;
u8 byte, bytex;

2
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
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@ -849,7 +849,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
u32 value;
u8 j;
u32 value_test;
u32 value_r, value_r_test;
u32 value_r = 0, value_r_test = 0;
u8 pattern, channel, BeatCnt;
struct DCTStatStruc *ptrAddr;

2
src/southbridge/amd/rs780/rs780.c
View File

@ -190,7 +190,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
{
/* NB_InitGFXStraps */
u32 MMIOBase, apc04, apc18, apc24, romstrap2;
msr_t pcie_mmio_save;
msr_t pcie_mmio_save = { 0, 0 };
volatile u32 * strap;
// disable processor pcie mmio, if enabled