Enable onboard VGA on the MS-6178 (i810 chipset) board (trivial).

Tested on hardware with the patch from r4398 and works fine as soon
as Linux boots (no VGA in FILO for some reason, will investigate).

In order to make the 'i810.vga' VGA blob from the vendor BIOS work
you have to make the check for PCI device ID mismatches non-fatal
(for now) in the src/devices/pci_rom.c file like this:

Index: src/devices/pci_rom.c
===================================================================
--- src/devices/pci_rom.c       (Revision 4393)
+++ src/devices/pci_rom.c       (Arbeitskopie)
@@ -87,7 +87,7 @@
        if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
                printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
                           rom_data->vendor, rom_data->device);
-               return NULL;
+               // return NULL;
        }

        printk_spew("PCI ROM Image,  Class Code %04x%02x, Code Type %02x\n",

The reason is that the VGA blob thinks the proper VGA device ID is 0x7123
whereas it really is 0x7121 on hardware. There are multiple ways to work
around this (there have been many discussions in the past), we'll see which
method will be used in future...

Note: This has been tested against r4393 only for now to make sure there
are no problems because of the recent resource allocator changes, see
http://www.coreboot.org/pipermail/coreboot/2009-July/050486.html.
Tests with trunk will follow.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/msi/ms6178/Config.lb

@@ -77,11 +77,9 @@ chip northbridge/intel/i82810			# Northbridge
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    device pci 1.0 off				# Onboard video
+    chip drivers/pci/onboard			# Onboard VGA
-      # chip drivers/pci/onboard
+      device pci 1.0 on end
-      #   device pci 1.0 on end
+      register "rom_address" = "0xfff80000"	# 512 KB image
-      #   register "rom_address" = "0xfff80000"
-      # end
     end
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"

src/mainboard/msi/ms6178/Options.lb

@@ -65,6 +65,7 @@ uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_HAVE_HIGH_TABLES
+uses CONFIG_VIDEO_MB
 
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_HAVE_FALLBACK_BOOT = 1
@@ -98,4 +99,5 @@ default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 default CONFIG_CBFS = 1
 default CONFIG_HAVE_HIGH_TABLES = 1
+default CONFIG_VIDEO_MB = 1
 end

src/mainboard/msi/ms6178/auto.c

@@ -36,6 +36,7 @@
 #include "cpu/x86/bist.h"
 #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
 #include "pc80/udelay_io.c"
+#include "lib/debug.c"
 #include "northbridge/intel/i82810/raminit.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

targets/msi/ms6178/Config.lb

@@ -33,6 +33,7 @@ option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 
 option CONFIG_CONSOLE_VGA = 1
 option CONFIG_PCI_ROM_RUN = 1
+option CONFIG_VIDEO_MB = 1
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE = 0
@@ -48,5 +49,5 @@ end
 
 buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
 
-# pci_rom i810.vga vendor_id=0x8086 device_id=0x7120
+pci_rom /tmp/i810.vga vendor_id=0x8086 device_id=0x7121