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mb/google/brya/anahera{4es}: Correct WWAN power sequence 

Correct the WWAN power sequence to meet spec

BUG=b:213021172
TEST=build

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Iab221fd03c637c82f6ce5c8278d432decf1b30c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wisley Chen 2021-12-29 11:38:57 +06:00 committed by Felix Held
parent 0de3e6570e
commit 328bfb3937
5 changed files with 40 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/brya/Kconfig.name
View File

@ -117,6 +117,7 @@ config BOARD_GOOGLE_ANAHERA
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_GFX_GENERIC
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select HAVE_WWAN_POWER_SEQUENCE
config BOARD_GOOGLE_ANAHERA4ES
bool "-> Anahera4ES"
@ -124,6 +125,7 @@ config BOARD_GOOGLE_ANAHERA4ES
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_GFX_GENERIC
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select HAVE_WWAN_POWER_SEQUENCE
config BOARD_GOOGLE_VELL
bool "-> Vell"

14
src/mainboard/google/brya/variants/anahera/gpio.c
View File

@ -57,6 +57,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E3, NONE),
/* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE),
/* E16 : RSVD_TP ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_E16, 1, DEEP),
/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
@ -90,11 +92,17 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_S6, NONE),
/* S7 : SNDW3_DATA ==> NC */
PAD_NC(GPP_S7, NONE),
/*
* E0 : SATAXPCIE0 ==> WWAN_PERST_L
* Drive high here, so that PERST_L is sequenced after RST_L
*/
PAD_CFG_GPO(GPP_E0, 1, DEEP),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
@ -124,6 +132,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
PAD_CFG_GPO(GPP_F21, 0, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
@ -143,6 +153,8 @@ static const struct pad_config early_gpio_table[] = {
static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
PAD_CFG_GPO(GPP_F21, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num)

6
src/mainboard/google/brya/variants/anahera/include/variant/gpio.h
View File

@ -5,4 +5,10 @@
#include <baseboard/gpio.h>
#define WWAN_FCPO GPP_F21
#define WWAN_RST GPP_E16
#define WWAN_PERST GPP_E0
#define T1_OFF_MS 16
#define T2_OFF_MS 2
#endif

14
src/mainboard/google/brya/variants/anahera4es/gpio.c
View File

@ -57,6 +57,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E3, NONE),
/* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE),
/* E16 : RSVD_TP ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_E16, 1, DEEP),
/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
@ -90,11 +92,17 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_S6, NONE),
/* S7 : SNDW3_DATA ==> NC */
PAD_NC(GPP_S7, NONE),
/*
* E0 : SATAXPCIE0 ==> WWAN_PERST_L
* Drive high here, so that PERST_L is sequenced after RST_L
*/
PAD_CFG_GPO(GPP_E0, 1, DEEP),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
@ -124,6 +132,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
PAD_CFG_GPO(GPP_F21, 0, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
@ -143,6 +153,8 @@ static const struct pad_config early_gpio_table[] = {
static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
PAD_CFG_GPO(GPP_F21, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num)

6
src/mainboard/google/brya/variants/anahera4es/include/variant/gpio.h
View File

@ -5,4 +5,10 @@
#include <baseboard/gpio.h>
#define WWAN_FCPO GPP_F21
#define WWAN_RST GPP_E16
#define WWAN_PERST GPP_E0
#define T1_OFF_MS 16
#define T2_OFF_MS 2
#endif