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cpu/intel: Drop SMM_TSEG conditional 

SMM_TSEG is a qualifier between TSEG and ASEG memory
region. ASEG is deprecated and not supported for
these CPUs in coreboot codebase.

Change-Id: I0602e04957a390473a2449e1c5ff951f9fdff73b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2019-07-08 09:16:13 +03:00
parent 8f076f2be8
commit 328d42f2d8
6 changed files with 6 additions and 6 deletions
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2
src/cpu/intel/model_1067x/Makefile.inc
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@ -2,6 +2,6 @@ ramstage-y += model_1067x_init.c
ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
subdirs-y += ../common subdirs-y += ../common
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 subdirs-y += ../smm/gen1
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*)

2
src/cpu/intel/model_106cx/Makefile.inc
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@ -1,7 +1,7 @@
ramstage-y += model_106cx_init.c ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
subdirs-y += ../common subdirs-y += ../common
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 subdirs-y += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*)

2
src/cpu/intel/model_6ex/Makefile.inc
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@ -1,7 +1,7 @@
ramstage-y += model_6ex_init.c ramstage-y += model_6ex_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
subdirs-y += ../common subdirs-y += ../common
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 subdirs-y += ../smm/gen1
ramstage-y += ../model_1067x/mp_init.c ramstage-y += ../model_1067x/mp_init.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0e-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0e-*)

2
src/cpu/intel/model_6fx/Makefile.inc
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@ -2,6 +2,6 @@ ramstage-y += model_6fx_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
subdirs-y += ../common subdirs-y += ../common
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 subdirs-y += ../smm/gen1
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*)

2
src/cpu/intel/model_f3x/Makefile.inc
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@ -1,5 +1,5 @@
ramstage-y += model_f3x_init.c ramstage-y += model_f3x_init.c
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 subdirs-y += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*)

2
src/cpu/intel/model_f4x/Makefile.inc
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@ -1,5 +1,5 @@
ramstage-y += model_f4x_init.c ramstage-y += model_f4x_init.c
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 subdirs-y += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*)