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soc/mediatek/mt8186: Adjust usage of SRAM L2C 

We use parts of SRAM_L2C as the memory of PRERAM_CBMEM_CONSOLE before
DRAM calibration. When we check cbmem, we found the content of this
memory is unreadable.

The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM
has configured only half of L2/L3 cache as SRAM. Therefore, decrease
the size of each SRAM region to fit into the first half of the cache.

BUG=b:207725851
TEST=Bootblock log looked good in `cbmem -c`

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Rex-BC Chen 2021-12-15 14:24:51 +08:00 committed by Felix Held
parent e226aabf79
commit 32992f264f
1 changed files with 11 additions and 5 deletions
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16
src/soc/mediatek/mt8186/include/soc/memlayout.ld
View File

@ -34,6 +34,12 @@ SECTIONS
/* MT8186 has 64KB SRAM. */ /* MT8186 has 64KB SRAM. */
SRAM_END(0x00110000) SRAM_END(0x00110000)
/*
* The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM
* has configured only half of L2/L3 cache as SRAM and the rest for cache
* so we can't use them unless if we disable L2C and reconfigure (be aware
* we can't configure whole L3 to SRAM without any cache).
*/
SRAM_L2C_START(0x00200000) SRAM_L2C_START(0x00200000)
/* 4K reserved for BOOTROM until BOOTBLOCK is started */ /* 4K reserved for BOOTROM until BOOTBLOCK is started */
BOOTBLOCK(0x00201000, 60K) BOOTBLOCK(0x00201000, 60K)
@ -41,11 +47,11 @@ SECTIONS
* The needed size can be obtained by: * The needed size can be obtained by:
* aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz
*/ */
DRAM_INIT_CODE(0x00210000, 240K) DRAM_INIT_CODE(0x00210000, 196K)
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00241000, 140K)
PRERAM_CBFS_CACHE(0x00290000, 48K) PRERAM_CBFS_CACHE(0x00264000, 48K)
PRERAM_CBMEM_CONSOLE(0x0029C000, 400K) PRERAM_CBMEM_CONSOLE(0x00270000, 64K)
SRAM_L2C_END(0x00300000) SRAM_L2C_END(0x00280000)
DRAM_START(0x40000000) DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M) DRAM_DMA(0x40000000, 1M)