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mb/google/brya/var/primus{4es}: Decrease touchscreen T3 timing to 200ms 

We set T3 as 300ms to meet Elan's spec, but the resume/suspend times
are greater than 500ms, which is the spec for Chromebooks.
The actual kernel timing has been measured, and given the ACPI delay
after deasserting reset in addition to the delay until the kernel
driver accesses the device, delaying only 200ms in the ACPI method is
also sufficient to meet the 300ms requirement.

BUG=b:223936777
BRANCH=none
TEST=build and test touchscreen function on DUT.
TEST=suspend, wake DUT and check touchscreen function.

Change-Id: I6b04cf6392d924aed01ca36b720f889b88d92311
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Casper Chang 2022-03-30 17:30:52 +08:00 committed by Paul Fagerburg
parent 390c3f2b47
commit 32a1d7ea8c
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/brya/variants/primus/overridetree.cb
View File

@ -221,7 +221,7 @@ chip soc/intel/alderlake
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
register "generic.reset_delay_ms" = "300"
register "generic.reset_delay_ms" = "200"
register "generic.reset_off_delay_ms" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"

2
src/mainboard/google/brya/variants/primus4es/overridetree.cb
View File

@ -208,7 +208,7 @@ chip soc/intel/alderlake
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
register "generic.reset_delay_ms" = "300"
register "generic.reset_delay_ms" = "200"
register "generic.reset_off_delay_ms" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"