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intel/pineview: Do not use scratchpad register for ACPI S3 

If S3 support was implemented for this platform later on, use
romstage handoff structure instead.

Change-Id: Ib0cf3ad41753baee26354c5ed19294048e7fb533
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15715
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
This commit is contained in:
Kyösti Mälkki 2016-07-15 13:51:22 +03:00
parent cbb23af2da
commit 32a38ee85b
2 changed files with 0 additions and 17 deletions
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1
src/northbridge/intel/pineview/early_init.c
View File

@ -206,7 +206,6 @@ static void pineview_setup_bars(void)
pci_write_config8(D0F0, PAM5, 0x33); pci_write_config8(D0F0, PAM5, 0x33);
pci_write_config8(D0F0, PAM6, 0x33); pci_write_config8(D0F0, PAM6, 0x33);
pci_write_config32(D0F0, SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, " done.\n");
} }

16
src/northbridge/intel/pineview/northbridge.c
View File

@ -177,22 +177,6 @@ static void enable_dev(device_t dev)
/* Set the operations if it is a special bus type */ /* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) { if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops; dev->ops = &pci_domain_ops;
#if CONFIG_HAVE_ACPI_RESUME
switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) {
case SKPAD_NORMAL_BOOT_MAGIC:
printk(BIOS_DEBUG, "Normal boot.\n");
acpi_slp_type=0;
break;
case SKPAD_ACPI_S3_MAGIC:
printk(BIOS_DEBUG, "S3 Resume.\n");
acpi_slp_type=3;
break;
default:
printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
acpi_slp_type=0;
break;
}
#endif
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops; dev->ops = &cpu_bus_ops;
} }