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nb/intel/i945: Use macro instead of magic number 

Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31027
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2019-01-21 14:54:31 +01:00 committed by Patrick Georgi
parent 8ed01a0e31
commit 32b9a99e16
3 changed files with 14 additions and 13 deletions
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4
src/northbridge/intel/i945/early_init.c
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@ -158,10 +158,10 @@ static void i945_setup_bars(void)
printk(BIOS_DEBUG, "Setting up static southbridge registers..."); printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN);
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN);
setup_pch_gpios(&mainboard_gpio_map); setup_pch_gpios(&mainboard_gpio_map);
printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, " done.\n");

22
src/northbridge/intel/i945/raminit.c
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@ -247,13 +247,13 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
u8 reg8; u8 reg8;
u8 do_reset = 0; u8 do_reset = 0;
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & ((1<<7)|(1<<2))) {
if (reg8 & (1<<2)) { if (reg8 & (1<<2)) {
printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
/* Write back clears bit 2 */ /* Write back clears bit 2 */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
do_reset = 1; do_reset = 1;
} }
@ -261,14 +261,14 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
if (reg8 & (1<<7)) { if (reg8 & (1<<7)) {
printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
reg8 &= ~(1<<7); reg8 &= ~(1<<7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
do_reset = 1; do_reset = 1;
} }
/* Set SLP_S3# Assertion Stretch Enable */ /* Set SLP_S3# Assertion Stretch Enable */
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
reg8 |= (1 << 3); reg8 |= (1 << 3);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
if (do_reset) { if (do_reset) {
printk(BIOS_DEBUG, "Reset required.\n"); printk(BIOS_DEBUG, "Reset required.\n");
@ -277,9 +277,9 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
} }
/* Set DRAM initialization bit in ICH7 */ /* Set DRAM initialization bit in ICH7 */
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
reg8 |= (1<<7); reg8 |= (1<<7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
/* clear self refresh status if check is disabled or not a resume */ /* clear self refresh status if check is disabled or not a resume */
if (!CONFIG(CHECK_SLFRCS_ON_RESUME) if (!CONFIG(CHECK_SLFRCS_ON_RESUME)
@ -1807,9 +1807,9 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
*/ */
goto cache_code; goto cache_code;
vco_update: vco_update:
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
reg8 &= ~(1 << 7); reg8 &= ~(1 << 7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
clkcfg &= ~(1 << 10); clkcfg &= ~(1 << 10);
MCHBAR32(CLKCFG) = clkcfg; MCHBAR32(CLKCFG) = clkcfg;
@ -2813,9 +2813,9 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
sdram_enable_rcomp(); sdram_enable_rcomp();
/* Tell ICH7 that we're done */ /* Tell ICH7 that we're done */
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
reg8 &= ~(1 << 7); reg8 &= ~(1 << 7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
printk(BIOS_DEBUG, "RAM initialization finished.\n"); printk(BIOS_DEBUG, "RAM initialization finished.\n");

1
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -94,6 +94,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
#define BIOS_CNTL 0xDC #define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
#define GPIO_EN (1 << 4)
#define PIRQA_ROUT 0x60 #define PIRQA_ROUT 0x60
#define PIRQB_ROUT 0x61 #define PIRQB_ROUT 0x61