nb/intel/i945: Use macro instead of magic number
Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31027 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -158,10 +158,10 @@ static void i945_setup_bars(void)
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printk(BIOS_DEBUG, "Setting up static southbridge registers...");
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */
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pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN);
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setup_pch_gpios(&mainboard_gpio_map);
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printk(BIOS_DEBUG, " done.\n");
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@ -247,13 +247,13 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
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u8 reg8;
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u8 do_reset = 0;
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
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if (reg8 & ((1<<7)|(1<<2))) {
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if (reg8 & (1<<2)) {
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printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
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/* Write back clears bit 2 */
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
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do_reset = 1;
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}
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@ -261,14 +261,14 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
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if (reg8 & (1<<7)) {
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printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
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reg8 &= ~(1<<7);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
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do_reset = 1;
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}
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/* Set SLP_S3# Assertion Stretch Enable */
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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reg8 |= (1 << 3);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
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if (do_reset) {
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printk(BIOS_DEBUG, "Reset required.\n");
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@ -277,9 +277,9 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
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}
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/* Set DRAM initialization bit in ICH7 */
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
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reg8 |= (1<<7);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
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/* clear self refresh status if check is disabled or not a resume */
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if (!CONFIG(CHECK_SLFRCS_ON_RESUME)
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@ -1807,9 +1807,9 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
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*/
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goto cache_code;
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vco_update:
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
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reg8 &= ~(1 << 7);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
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clkcfg &= ~(1 << 10);
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MCHBAR32(CLKCFG) = clkcfg;
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@ -2813,9 +2813,9 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
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sdram_enable_rcomp();
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/* Tell ICH7 that we're done */
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
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reg8 &= ~(1 << 7);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
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printk(BIOS_DEBUG, "RAM initialization finished.\n");
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@ -94,6 +94,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
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#define BIOS_CNTL 0xDC
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#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
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#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
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#define GPIO_EN (1 << 4)
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#define PIRQA_ROUT 0x60
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#define PIRQB_ROUT 0x61
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