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mb/intel/coffeelake_rvp: Use CHIPSET_LOCKDOWN_COREBOOT 

Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown on all variants.

Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2021-07-17 04:58:16 +02:00 committed by Nico Huber
parent ca3aa52cf8
commit 32ca3ac9ab
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
View File

@ -1,5 +1,7 @@
chip soc/intel/cannonlake
register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
device cpu_cluster 0 on
device lapic 0 on end
end

2
src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
View File

@ -48,11 +48,9 @@ chip soc/intel/cannonlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C3 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[3] = {
.speed = I2C_SPEED_STANDARD,
.rise_time_ns = 104,