ec/google/chromeec: Use common MEC interface
Switch to using the common MEC interface instead of the Chrome EC specific code. Tested on a Chell chromebook that has a MEC based Chrome EC to ensure that the EC interface is still functional. Change-Id: Idf26e62c2843993c2df2ab8ef157b263a71a97c9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -56,6 +56,7 @@ config EC_GOOGLE_CHROMEEC_LPC
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config EC_GOOGLE_CHROMEEC_MEC
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depends on EC_GOOGLE_CHROMEEC_LPC
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def_bool n
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select EC_GOOGLE_COMMON_MEC
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help
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Microchip EC variant for LPC register access.
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@ -7,26 +7,21 @@ smm-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c
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bootblock-y += ec.c
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bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c
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ramstage-y += ec.c crosec_proto.c vstore.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
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smm-y += ec.c crosec_proto.c smihandler.c vstore.c
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smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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smm-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c
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smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
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romstage-y += ec.c crosec_proto.c vstore.c
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romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c
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romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
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verstage-y += ec.c crosec_proto.c vstore.c
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verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c
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verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
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ramstage-$(CONFIG_VBOOT) += vboot_storage.c
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@ -93,9 +93,6 @@ int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize);
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#define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0
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#define MEC_EMI_RANGE_END (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE)
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void mec_io_bytes(int write, u16 offset, unsigned int length,
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u8 *buf, u8 *csum);
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enum usb_charge_mode {
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USB_CHARGE_MODE_DISABLED,
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USB_CHARGE_MODE_CHARGE_AUTO,
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@ -18,6 +18,7 @@
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#include <console/console.h>
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#include <delay.h>
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#include <device/pnp.h>
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#include <ec/google/common/mec.h>
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#include <stdint.h>
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#include <stdlib.h>
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@ -40,7 +41,9 @@ static void read_bytes(u16 port, unsigned int length, u8 *dest, u8 *csum)
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#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)
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/* Access desired range though EMI interface */
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if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) {
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mec_io_bytes(0, port, length, dest, csum);
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csum += mec_io_bytes(MEC_IO_READ, MEC_EMI_BASE,
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port - MEC_EMI_RANGE_START,
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dest, length);
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return;
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}
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#endif
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@ -75,7 +78,9 @@ static void write_bytes(u16 port, unsigned int length, u8 *msg, u8 *csum)
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#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)
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/* Access desired range though EMI interface */
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if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) {
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mec_io_bytes(1, port, length, msg, csum);
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csum += mec_io_bytes(MEC_IO_WRITE, MEC_EMI_BASE,
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port - MEC_EMI_RANGE_START,
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msg, length);
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return;
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}
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#endif
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@ -1,125 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include "ec.h"
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#include "ec_commands.h"
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enum {
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/* 8-bit access */
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ACCESS_TYPE_BYTE = 0x0,
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/* 16-bit access */
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ACCESS_TYPE_WORD = 0x1,
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/* 32-bit access */
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ACCESS_TYPE_LONG = 0x2,
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/*
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* 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the
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* EC data register to be incremented.
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*/
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ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3,
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};
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/* EMI registers are relative to base */
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#define MEC_EMI_HOST_TO_EC (MEC_EMI_BASE + 0)
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#define MEC_EMI_EC_TO_HOST (MEC_EMI_BASE + 1)
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#define MEC_EMI_EC_ADDRESS_B0 (MEC_EMI_BASE + 2)
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#define MEC_EMI_EC_ADDRESS_B1 (MEC_EMI_BASE + 3)
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#define MEC_EMI_EC_DATA_B0 (MEC_EMI_BASE + 4)
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#define MEC_EMI_EC_DATA_B1 (MEC_EMI_BASE + 5)
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#define MEC_EMI_EC_DATA_B2 (MEC_EMI_BASE + 6)
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#define MEC_EMI_EC_DATA_B3 (MEC_EMI_BASE + 7)
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/*
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* cros_ec_lpc_mec_emi_write_address
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*
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* Initialize EMI read / write at a given address.
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*
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* @addr: Starting read / write address
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* @access_mode: Type of access, typically 32-bit auto-increment
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*/
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static void mec_emi_write_address(u16 addr, u8 access_mode)
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{
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/* Address relative to start of EMI range */
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addr -= MEC_EMI_RANGE_START;
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outb((addr & 0xfc) | access_mode, MEC_EMI_EC_ADDRESS_B0);
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outb((addr >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1);
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}
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/*
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* mec_io_bytes - Read / write bytes to MEC EMI port
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*
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* @write: 1 on write operation, 0 on read
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* @port: Base read / write address
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* @length: Number of bytes to read / write
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* @buf: Destination / source buffer
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* @csum: Optional parameter, sums data transferred
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*
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*/
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void mec_io_bytes(int write, u16 port, unsigned int length, u8 *buf, u8 *csum)
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{
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int i = 0;
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int io_addr;
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u8 access_mode, new_access_mode;
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if (length == 0)
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return;
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/*
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* Long access cannot be used on misaligned data since reading B0 loads
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* the data register and writing B3 flushes it.
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*/
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if ((port & 0x3) || (length < 4))
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access_mode = ACCESS_TYPE_BYTE;
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else
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access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT;
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/* Initialize I/O at desired address */
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mec_emi_write_address(port, access_mode);
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/* Skip bytes in case of misaligned port */
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io_addr = MEC_EMI_EC_DATA_B0 + (port & 0x3);
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while (i < length) {
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while (io_addr <= MEC_EMI_EC_DATA_B3) {
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if (write)
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outb(buf[i], io_addr++);
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else
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buf[i] = inb(io_addr++);
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if (csum)
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*csum += buf[i];
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port++;
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/* Extra bounds check in case of misaligned length */
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if (++i == length)
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return;
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}
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/*
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* Use long auto-increment access except for misaligned write,
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* since writing B3 triggers the flush.
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*/
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if (length - i < 4 && write)
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new_access_mode = ACCESS_TYPE_BYTE;
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else
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new_access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT;
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if (new_access_mode != access_mode ||
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access_mode != ACCESS_TYPE_LONG_AUTO_INCREMENT) {
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access_mode = new_access_mode;
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mec_emi_write_address(port, access_mode);
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}
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/* Access [B0, B3] on each loop pass */
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io_addr = MEC_EMI_EC_DATA_B0;
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}
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}
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