soc/intel/common/cse: Rework heci_disable function

This patch provides the possible options for SoC users to choose the
applicable interface to make HECI1 function disable at pre-boot.

`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for
disabling heci1 using non-posted sideband write (inside SMM) after
FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.

`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for
disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH
onwards.

`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for
disabling heci1 using private configuration register (PCR) write.
Applicable for SoC platform prior to CNL PCH.

Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the
compilation failure.

Finally, rename heci_disable() function to heci1_disable() to make it
more meaningful.

BUG=none
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>

src/soc/intel/alderlake/smihandler.c

@@ -20,7 +20,7 @@ void smihandler_soc_at_finalize(void)
 		return;
 
 	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
-		heci_disable();
+		heci1_disable();
 }
 
 int smihandler_soc_disable_busmaster(pci_devfn_t dev)

src/soc/intel/apollolake/include/soc/pcr_ids.h

@@ -27,5 +27,6 @@
 
 #define PID_PSF3	0xC6
 #define PID_DMI	0x00 /* Reserved */
+#define PID_CSME0	0x9A /* Reserved */
 
 #endif	/* SOC_INTEL_APL_PCR_H */

src/soc/intel/cannonlake/smihandler.c

@@ -17,7 +17,7 @@
 void smihandler_soc_at_finalize(void)
 {
 	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
-		heci_disable();
+		heci1_disable();
 }
 
 const smi_handler_t southbridge_smi[SMI_STS_BITS] = {

src/soc/intel/common/block/cse/Kconfig

@@ -14,13 +14,32 @@ config DISABLE_HECI1_AT_PRE_BOOT
 	  Mainboard users to select this config to make HECI1 `function disable`
 	  prior to handing off to payload.
 
-config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM
+config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI
 	bool
 	default y if HECI_DISABLE_USING_SMM
 	select SOC_INTEL_COMMON_BLOCK_P2SB
 	help
-	  Use this config to include common CSE block to make HECI function
-	  disable in SMM mode
+	  Use this config to allow common CSE block to make HECI1 function disable
+	  in the SMM mode. From CNL PCH onwards,`HECI1` disabling can only be done
+	  using the non-posted sideband write after FSP-S sets the postboot_sai
+	  attribute.
+
+config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
+	bool
+	default n
+	select SOC_INTEL_COMMON_BLOCK_PMC
+	help
+	  Use this config to allow common CSE block to make HECI1 function disable
+	  using PMC IPC command `0xA9`. From TGL PCH onwards, disabling heci1
+	  device using PMC IPC doesn't required to run the operation in SMM.
+
+config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
+	bool
+	default n
+	select SOC_INTEL_COMMON_BLOCK_PCR
+	help
+	  Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented)
+	  to make `HECI1` device disable using private configuration register (PCR) write.
 
 config SOC_INTEL_CSE_LITE_SKU
 	bool

src/soc/intel/common/block/cse/Makefile.inc

@@ -2,7 +2,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
 romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
 ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
-smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c
 
 ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c
 

src/soc/intel/common/block/cse/disable_heci.c

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#define __SIMPLE_DEVICE__
+
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <device/pci.h>
@@ -15,8 +17,20 @@
 #define CSME0_BAR	0x0
 #define CSME0_FID	0xb0
 
+/* Disable HECI using PCR */
+static void heci1_disable_using_pcr(void)
+{
+	soc_disable_heci1_using_pcr();
+}
+
+/* Disable HECI using PMC IPC communication */
+static void heci1_disable_using_pmc(void)
+{
+	cse_disable_mei_devices();
+}
+
 /* Disable HECI using Sideband interface communication */
-void heci_disable(void)
+static void heci1_disable_using_sbi(void)
 {
 	struct pcr_sbi_msg msg = {
 		.pid = PID_CSME0,
@@ -46,3 +60,23 @@ void heci_disable(void)
 	/* hide p2sb device */
 	p2sb_hide();
 }
+
+void heci1_disable(void)
+{
+	if (!CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+		return;
+
+	if (ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI)) {
+		printk(BIOS_INFO, "Disabling Heci using SBI in SMM mode\n");
+		return heci1_disable_using_sbi();
+	} else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) {
+		printk(BIOS_INFO, "Disabling Heci using PMC IPC\n");
+		return heci1_disable_using_pmc();
+	} else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR)) {
+		printk(BIOS_INFO, "Disabling Heci using PCR\n");
+		return heci1_disable_using_pcr();
+	} else {
+		printk(BIOS_ERR, "%s Error: Unable to make HECI1 function disable!\n",
+				__func__);
+	}
+}

src/soc/intel/common/block/include/intelblocks/cse.h

@@ -311,8 +311,8 @@ int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t
  * Returns 0 on failure and 1 on success.
  */
 int heci_reset(void);
-/* Disable HECI using Sideband interface communication */
-void heci_disable(void);
+/* Disable HECI1 using Sideband interface communication */
+void heci1_disable(void);
 
 /* Reads config value from a specified offset in the CSE PCI Config space. */
 uint32_t me_read_config32(int offset);
@@ -489,4 +489,12 @@ bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf);
 /* Function to make cse disable using PMC IPC */
 bool cse_disable_mei_devices(void);
 
+/*
+ * SoC override API to make heci1 disable using PCR.
+ *
+ * Allow SoC to implement heci1 disable override due to PSF registers being
+ * different across SoC generation.
+ */
+void soc_disable_heci1_using_pcr(void);
+
 #endif // SOC_INTEL_COMMON_CSE_H

src/soc/intel/elkhartlake/smihandler.c

@@ -17,7 +17,7 @@
 void smihandler_soc_at_finalize(void)
 {
 	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
-		heci_disable();
+		heci1_disable();
 }
 
 const smi_handler_t southbridge_smi[SMI_STS_BITS] = {

src/soc/intel/icelake/smihandler.c

@@ -17,7 +17,7 @@
 void smihandler_soc_at_finalize(void)
 {
 	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
-		heci_disable();
+		heci1_disable();
 }
 
 const smi_handler_t southbridge_smi[SMI_STS_BITS] = {

src/soc/intel/jasperlake/smihandler.c

@@ -17,7 +17,7 @@
 void smihandler_soc_at_finalize(void)
 {
 	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
-		heci_disable();
+		heci1_disable();
 }
 
 int smihandler_soc_disable_busmaster(pci_devfn_t dev)

src/soc/intel/skylake/include/soc/pcr_ids.h

@@ -7,6 +7,7 @@
  * Port ids
  */
 #define PID_PSTH	0x89
+#define PID_CSME0	0x90
 #define PID_GPIOCOM3	0xAC
 #define PID_GPIOCOM2	0xAD
 #define PID_GPIOCOM1	0xAE

src/soc/intel/tigerlake/smihandler.c

@@ -17,7 +17,7 @@
 void smihandler_soc_at_finalize(void)
 {
 	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
-		heci_disable();
+		heci1_disable();
 }
 
 int smihandler_soc_disable_busmaster(pci_devfn_t dev)

src/soc/intel/xeon_sp/include/soc/pcr_ids.h

@@ -3,6 +3,7 @@
 #ifndef _PCR_IDS_H_
 #define _PCR_IDS_H_
 
+#define PID_CSME0	0x90
 #define PID_ITSS	0xC4
 #define PID_RTC		0xC3
 #define PID_DMI		0xEF