mb/google/brask/variants/moli: correct empty tcss port
Correct empty tcss port to meet Moli's schematic design. BUG=b:233834605 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Id16744655010e246c8ca8d1050f71a6c6c63d2a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -24,7 +24,7 @@ chip soc/intel/alderlake
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2 Port3
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2 Port3
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register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # Enable USB2 Port4
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register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # Enable USB2 Port4
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9
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register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP3
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register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3
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register "cnvi_bt_audio_offload" = "true"
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register "cnvi_bt_audio_offload" = "true"
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device domain 0 on
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device domain 0 on
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device ref tcss_dma0 on
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device ref tcss_dma0 on
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