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mb/google/brask/variants/moli: correct empty tcss port 

Correct empty tcss port to meet Moli's schematic design.

BUG=b:233834605
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Id16744655010e246c8ca8d1050f71a6c6c63d2a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Raihow Shi 2022-05-25 14:47:13 +08:00 committed by Martin L Roth
parent 455accd3f7
commit 32e72ca0b7
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/brya/variants/moli/overridetree.cb
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@ -24,7 +24,7 @@ chip soc/intel/alderlake
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2 Port3
register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # Enable USB2 Port4
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9
register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP3
register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3
register "cnvi_bt_audio_offload" = "true"
device domain 0 on
device ref tcss_dma0 on