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soc/amd/cezanne: Add device tree support for I2C 

This allows the cr50 on guybrush to show up in ACPI.

BUG=b:183737011
TEST=Boot OS and see I2C devices initialized

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2021-03-30 15:56:46 -06:00 committed by Felix Held
parent f63f2f291b
commit 32fc4e350b
1 changed files with 8 additions and 0 deletions
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8
src/soc/amd/cezanne/chip.c
View File

@ -10,6 +10,8 @@
#include <types.h>
#include "chip.h"
/* Supplied by i2c.c */
extern struct device_operations soc_amd_i2c_mmio_ops;
/* Supplied by uart.c */
extern struct device_operations cezanne_uart_mmio_ops;
@ -42,6 +44,12 @@ static struct device_operations pci_domain_ops = {
static void set_mmio_dev_ops(struct device *dev)
{
switch (dev->path.mmio.addr) {
case APU_I2C0_BASE:
case APU_I2C1_BASE:
case APU_I2C2_BASE:
case APU_I2C3_BASE:
dev->ops = &soc_amd_i2c_mmio_ops;
break;
case APU_UART0_BASE:
case APU_UART1_BASE:
dev->ops = &cezanne_uart_mmio_ops;