From 330dc10cfd956df91855593b6f33b502c6883c55 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Thu, 9 Nov 2017 15:00:54 +0530
Subject: [PATCH] soc/intel/apollolake: Include HECI BAR0 address inside
 iomap.h

This ensures HECI1_BASE_ADDRESS macro is coming from respective
SoC dirctory and not hardcoded inside common cse code. As per
firmware specification HECI1_BASE_ADDRESS might be different
between different socs.

Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/apollolake/include/soc/iomap.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index c3eb66bef6..d4cd0952e8 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -44,6 +44,8 @@
 #define SRAM_BASE_2			0xfe902000
 #define SRAM_SIZE_2			(4 * KiB)
 
+#define HECI1_BASE_ADDRESS		0xfed1a000
+
 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
 #define PRERAM_SPI_BASE_ADDRESS		0xfe010000