diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a65bb6d7a8..852dfadaf0 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1e6aafdbcd..1d5bac8ddb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -14,7 +14,6 @@ bootblock-y += car.c bootblock-y += flash_ctrlr.c bootblock-y += gpio.c bootblock-y += heci.c -bootblock-y += itss.c bootblock-y += lpc_lib.c bootblock-y += mmap_boot.c bootblock-y += pmutil.c @@ -29,7 +28,6 @@ romstage-y += flash_ctrlr.c romstage-y += gpio.c romstage-y += heci.c romstage-y += i2c_early.c -romstage-y += itss.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c romstage-y += memmap.c @@ -60,7 +58,6 @@ ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += heci.c ramstage-y += i2c.c -ramstage-y += itss.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += lpc.c ramstage-y += lpc_lib.c diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 8aed7b68aa..3108987329 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -26,12 +26,13 @@ #include #include #include +#include #include #include +#include #include #include #include -#include #include #include #include diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index d9957726eb..c2375062f7 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -17,9 +17,9 @@ #include #include +#include #include #include -#include #include #include diff --git a/src/soc/intel/apollolake/include/soc/itss.h b/src/soc/intel/apollolake/include/soc/itss.h index 2f47ec6259..e61f2d224a 100644 --- a/src/soc/intel/apollolake/include/soc/itss.h +++ b/src/soc/intel/apollolake/include/soc/itss.h @@ -16,14 +16,11 @@ #ifndef _SOC_APOLLOLAKE_ITSS_H_ #define _SOC_APOLLOLAKE_ITSS_H_ -#define GPIO_IRQ_START 50 -#define GPIO_IRQ_END 119 +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ -/* Set the interrupt polarity for provided IRQ to the APIC. */ -void itss_set_irq_polarity(int irq, int active_low); - -/* Snapshot and restore IRQ polarity settings for the inclusive range. */ -void itss_snapshot_irq_polarities(int start, int end); -void itss_restore_irq_polarities(int start, int end); +#define ITSS_MAX_IRQ 119 +#define IRQS_PER_IPC 32 +#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) #endif /* _SOC_APOLLOLAKE_ITSS_H_ */ diff --git a/src/soc/intel/apollolake/itss.c b/src/soc/intel/apollolake/itss.c deleted file mode 100644 index 17b197547f..0000000000 --- a/src/soc/intel/apollolake/itss.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#define ITSS_MAX_IRQ 119 -#define IRQS_PER_IPC 32 -#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) -#define PCR_IPC0_CONF 0x3200 - -void itss_set_irq_polarity(int irq, int active_low) -{ - uint32_t mask; - uint16_t reg; - const uint16_t port = PID_ITSS; - - if (irq < 0 || irq > ITSS_MAX_IRQ) - return; - - reg = PCR_IPC0_CONF + sizeof(uint32_t) * (irq / IRQS_PER_IPC); - mask = 1 << (irq % IRQS_PER_IPC); - - pcr_rmw32(port, reg, ~mask, (active_low ? mask : 0)); -} - -static uint32_t irq_snapshot[NUM_IPC_REGS]; - -void itss_snapshot_irq_polarities(int start, int end) -{ - int i; - int reg_start; - int reg_end; - const uint16_t port = PID_ITSS; - - if (start < 0 || start > ITSS_MAX_IRQ || - end < 0 || end > ITSS_MAX_IRQ || end < start) - return; - - reg_start = start / IRQS_PER_IPC; - reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; - - for (i = reg_start; i < reg_end; i++) { - uint16_t reg = PCR_IPC0_CONF + sizeof(uint32_t) * i; - irq_snapshot[i] = pcr_read32(port, reg); - } -} - -static void show_irq_polarities(const char *msg) -{ - int i; - const uint16_t port = PID_ITSS; - - printk(BIOS_INFO, "ITSS IRQ Polarities %s:\n", msg); - for (i = 0; i < NUM_IPC_REGS; i++) { - uint16_t reg = PCR_IPC0_CONF + sizeof(uint32_t) * i; - printk(BIOS_INFO, "IPC%d: 0x%08x\n", i, pcr_read32(port, reg)); - } -} - -void itss_restore_irq_polarities(int start, int end) -{ - int i; - int reg_start; - int reg_end; - const uint16_t port = PID_ITSS; - - if (start < 0 || start > ITSS_MAX_IRQ || - end < 0 || end > ITSS_MAX_IRQ || end < start) - return; - - show_irq_polarities("Before"); - - reg_start = start / IRQS_PER_IPC; - reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; - - for (i = reg_start; i < reg_end; i++) { - uint32_t mask; - uint16_t reg; - int irq_start; - int irq_end; - - irq_start = i * IRQS_PER_IPC; - irq_end = MIN(irq_start + IRQS_PER_IPC - 1, ITSS_MAX_IRQ); - - if (start > irq_end) - continue; - if (end < irq_start) - break; - - /* Track bits within the bounds of of the register. */ - irq_start = MAX(start, irq_start) % IRQS_PER_IPC; - irq_end = MIN(end, irq_end) % IRQS_PER_IPC; - - /* Create bitmask of the inclusive range of start and end. */ - mask = (((1U << irq_end) - 1) | (1U << irq_end)); - mask &= ~((1U << irq_start) - 1); - - reg = PCR_IPC0_CONF + sizeof(uint32_t) * i; - pcr_rmw32(port, reg, ~mask, (mask & irq_snapshot[i])); - } - - show_irq_polarities("After"); -}