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nb/intel: add IS_ENABLED() around Kconfig symbol references 

Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Martin Roth 2017-06-24 14:48:50 -06:00
parent 71693ba43f
commit 33232604a7
28 changed files with 48 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/northbridge/intel/e7505/raminit.c
View File

@ -41,7 +41,7 @@ Definitions:
// Unfortunately the code seems to chew up several K of space.
//#define VALIDATE_DIMM_COMPATIBILITY
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
@ -1003,7 +1003,7 @@ static inline void __attribute__((always_inline))
::: "edi"
);
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
unsigned int a1, a2;
asm volatile("movd %%xmm2, %%eax;" : "=a" (a1) ::);
asm volatile("movd %%xmm3, %%eax;" : "=a" (a2) ::);

2
src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
View File

@ -33,7 +33,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
#if CONFIG_CHROMEOS_RAMOOPS
#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif

4
src/northbridge/intel/fsp_sandybridge/early_init.c
View File

@ -42,7 +42,7 @@ static void sandybridge_setup_bars(void)
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@ -51,7 +51,7 @@ static void sandybridge_setup_bars(void)
printk(BIOS_DEBUG, " done.\n");
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)

2
src/northbridge/intel/haswell/acpi/haswell.asl
View File

@ -33,7 +33,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
#if CONFIG_CHROMEOS_RAMOOPS
#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif

2
src/northbridge/intel/haswell/gma.c
View File

@ -30,7 +30,7 @@
#include "chip.h"
#include "haswell.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#endif

2
src/northbridge/intel/haswell/northbridge.c
View File

@ -368,7 +368,7 @@ static void mc_add_dram_resources(device_t dev)
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
(0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS
#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);

2
src/northbridge/intel/i440bx/debug.c
View File

@ -5,7 +5,7 @@
#include <spd.h>
#include <console/console.h>
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
void dump_spd_registers(void)
{
int i;

4
src/northbridge/intel/i440bx/raminit.c
View File

@ -32,7 +32,7 @@ Macros and definitions.
#define NB PCI_DEV(0, 0, 0)
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x)
#define DUMPNORTH() dump_pci_device(NB)
#else
@ -301,7 +301,7 @@ static const u8 register_values[] = {
* 0 = 3 clocks of RAS# precharge
* 1 = 2 clocks of RAS# precharge
*/
#if CONFIG_SDRAMPWR_4DIMM
#if IS_ENABLED(CONFIG_SDRAMPWR_4DIMM)
SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */
#else
SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots. */

2
src/northbridge/intel/i440bx/raminit.h
View File

@ -26,7 +26,7 @@ void sdram_set_registers(void);
void sdram_set_spd_registers(void);
void sdram_enable(void);
/* Debug */
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
void dump_spd_registers(void);
void dump_pci_device(unsigned dev);
#else

2
src/northbridge/intel/i5000/raminit.c
View File

@ -1752,7 +1752,7 @@ void i5000_fbdimm_init(void)
if (setup.branch[1].used)
i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK)
if (ram_check_nodie(0x000000, 0x0a0000) ||
ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xd0000000))) {
i5000_try_restart("RAM verification failed");

2
src/northbridge/intel/i82810/debug.c
View File

@ -5,7 +5,7 @@
#include <spd.h>
#include <console/console.h>
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
void dump_spd_registers(void)
{
int i;

2
src/northbridge/intel/i82810/raminit.c
View File

@ -30,7 +30,7 @@ Macros and definitions.
-----------------------------------------------------------------------------*/
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else

2
src/northbridge/intel/i82810/raminit.h
View File

@ -26,7 +26,7 @@ void sdram_set_spd_registers(void);
void sdram_enable(void);
/* Debug */
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
void dump_spd_registers(void);
void dump_pci_device(unsigned dev);
#else

2
src/northbridge/intel/i82830/raminit.c
View File

@ -25,7 +25,7 @@ Macros and definitions.
-----------------------------------------------------------------------------*/
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else

2
src/northbridge/intel/i82830/smihandler.c
View File

@ -31,7 +31,7 @@ extern u32 mbi_len;
/* If YABEL is enabled and it's not running at 0x00000000, we have to add some
* offset to all our mbi object memory accesses
*/
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && !CONFIG_YABEL_DIRECTHW
#define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION
#else
#define OBJ_OFFSET 0x00000

2
src/northbridge/intel/i82830/vga.c
View File

@ -43,7 +43,7 @@ static void vga_init(device_t dev)
printk(BIOS_INFO, "Graphics Initialization Complete\n");
/* Enable TV-Out */
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
#define PIPE_A_CRT (1 << 0)
#define PIPE_A_LFP (1 << 1)
#define PIPE_A_TV (1 << 3)

6
src/northbridge/intel/i855/raminit.c
View File

@ -29,7 +29,7 @@ Macros and definitions:
#define VALIDATE_DIMM_COMPATIBILITY
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
#define DUMPNORTH() dump_pci_device(NORTHBRIDGE_MMC)
#else
@ -868,11 +868,11 @@ static void spd_set_dram_throttle_control(void)
static void spd_update(u8 reg, u32 new_value)
{
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
u32 value1 = pci_read_config32(NORTHBRIDGE_MMC, reg);
#endif
pci_write_config32(NORTHBRIDGE_MMC, reg, new_value);
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg);
PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
#endif

4
src/northbridge/intel/i945/early_init.c
View File

@ -944,9 +944,9 @@ void i945_late_initialization(int s3resume)
i945_setup_root_complex_topology();
#if !CONFIG_HAVE_ACPI_RESUME
#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
sdram_dump_mchbar_registers();
{

20
src/northbridge/intel/i945/raminit.c
View File

@ -30,7 +30,7 @@
#include <cbmem.h>
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
#else
#define PRINTK_DEBUG(x...)
@ -93,7 +93,7 @@ static void ram_read32(u32 offset)
read32((void *)offset);
}
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
void sdram_dump_mchbar_registers(void)
{
int i;
@ -1075,7 +1075,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index)
return nc;
}
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)
/* Strength multiplier tables */
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@ -1130,7 +1130,7 @@ static const u8 single_channel_strength_multiplier[] = {
0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
};
#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@ -2255,7 +2255,7 @@ static void sdram_program_clock_crossing(void)
/**
* We add the indices according to our clocks from CLKCFG.
*/
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)
static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistent */
@ -2300,7 +2300,7 @@ static void sdram_program_clock_crossing(void)
0xffffffff, 0xffffffff, /* nonexistent */
};
#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)
/* i945 G/P */
static const u32 data_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistent */
@ -2520,7 +2520,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
if (sysinfo->interleaved) {
reg32 = MCHBAR32(DCC);
#if CONFIG_CHANNEL_XOR_RANDOMIZATION
#if IS_ENABLED(CONFIG_CHANNEL_XOR_RANDOMIZATION)
reg32 &= ~(1 << 10);
reg32 |= (1 << 9);
#else
@ -2897,9 +2897,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
{
u8 clocks[2] = { 0, 0 };
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)
#define CLOCKS_WIDTH 2
#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)
#define CLOCKS_WIDTH 3
#endif
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
@ -2914,7 +2914,7 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
#if CONFIG_OVERRIDE_CLOCK_DISABLE
#if IS_ENABLED(CONFIG_OVERRIDE_CLOCK_DISABLE)
/* Usually system firmware turns off system memory clock signals
* to unused SO-DIMM slots to reduce EMI and power consumption.
* However, the Kontron 986LCD-M does not like unused clock

2
src/northbridge/intel/i945/raminit.h
View File

@ -68,7 +68,7 @@ void sdram_initialize(int boot_path, const u8 *sdram_addresses);
int fixup_i945_errata(void);
void udelay(u32 us);
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
void sdram_dump_mchbar_registers(void);
#endif
#endif /* RAMINIT_H */

2
src/northbridge/intel/nehalem/acpi/nehalem.asl
View File

@ -33,7 +33,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
#if CONFIG_CHROMEOS_RAMOOPS
#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif

4
src/northbridge/intel/nehalem/early_init.c
View File

@ -72,7 +72,7 @@ static void nehalem_setup_bars(void)
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33);
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@ -81,7 +81,7 @@ static void nehalem_setup_bars(void)
printk(BIOS_DEBUG, " done.\n");
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)

2
src/northbridge/intel/nehalem/northbridge.c
View File

@ -80,7 +80,7 @@ static void add_fixed_resources(struct device *dev, int index)
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
(0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS
#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);

6
src/northbridge/intel/pineview/raminit.c
View File

@ -28,7 +28,7 @@
#include <string.h>
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
#else
#define PRINTK_DEBUG(x...)
@ -134,7 +134,7 @@ static int decode_spd(struct dimminfo *d, int i)
d->tRCD = d->spd_data[29];
d->tWR = d->spd_data[36];
d->ranks = d->sides; // XXX
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
const char *ubso[2] = { "UB", "SO" };
#endif
PRINTK_DEBUG("%s-DIMM %d\n", &ubso[d->type][0], i);
@ -318,7 +318,7 @@ static void sdram_read_spds(struct sysinfo *s)
}
}
#if CONFIG_DEBUG_RAM_SETUP
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
static u32 fsb_reg_to_mhz(u32 speed)
{
return (speed * 133) + 667;

2
src/northbridge/intel/sandybridge/acpi/sandybridge.asl
View File

@ -33,7 +33,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
#if CONFIG_CHROMEOS_RAMOOPS
#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif

4
src/northbridge/intel/sandybridge/early_init.c
View File

@ -60,7 +60,7 @@ static void sandybridge_setup_bars(void)
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@ -69,7 +69,7 @@ static void sandybridge_setup_bars(void)
printk(BIOS_DEBUG, " done.\n");
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)

2
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -100,7 +100,7 @@ static void add_fixed_resources(struct device *dev, int index)
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
(0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS
#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);

4
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@ -39,7 +39,7 @@
* MRC scrambler seed offsets should be reserved in
* mainboard cmos.layout and not covered by checksum.
*/
#if CONFIG_USE_OPTION_TABLE
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
#include "option_table.h"
#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3)
#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)
@ -236,7 +236,7 @@ void sdram_initialize(struct pei_data *pei_data)
die("UEFI PEI System Agent not found.\n");
}
#if CONFIG_USBDEBUG_IN_ROMSTAGE
#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
/* mrc.bin reconfigures USB, so reinit it to have debug */
usbdebug_init();
#endif