GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

broadwell: Compute channel disable masks at runtime 

Introduce the `SPD_MEMORY_DOWN` macro to indicate that a slot is used
with memory-down. This enables computing the channel disable masks as
the bits for slots where the SPD address is zero. To preserve current
behavior, zero the SPD addresses for memory-down slots afterwards.

Change-Id: I75b7be7c72062d1a26cfc7b09b79de62de0a9cea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55807
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-06-23 14:39:32 +02:00
parent eb80d8da88
commit 333751b22e
13 changed files with 26 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/mainboard/google/auron/spd.c
View File

@ -104,9 +104,10 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
const unsigned int spd_index = variant_get_spd_index();
fill_spd_for_index(pei_data->spd_data[0][0], spd_index);
pei_data->spd_addresses[0] = SPD_MEMORY_DOWN;
if (variant_is_dual_channel(spd_index))
if (variant_is_dual_channel(spd_index)) {
memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN);
else
pei_data->dimm_channel1_disabled = 3;
pei_data->spd_addresses[2] = SPD_MEMORY_DOWN;
}
}

4
src/mainboard/google/auron/variants/auron_paine/pei_data.c
View File

@ -7,10 +7,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
/* One installed DIMM per channel -- can be changed by SPD init */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */

4
src/mainboard/google/auron/variants/auron_yuna/pei_data.c
View File

@ -7,10 +7,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
/* One installed DIMM per channel -- can be changed by SPD init */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */

2
src/mainboard/google/auron/variants/buddy/spd/spd.c
View File

@ -9,8 +9,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
{
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
/* Enable 2x refresh mode */
pei_data->ddr_refresh_2x = 1;
pei_data->dq_pins_interleaved = 1;

4
src/mainboard/google/auron/variants/gandof/pei_data.c
View File

@ -7,10 +7,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
/* One installed DIMM per channel -- can be changed by SPD init */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */

4
src/mainboard/google/auron/variants/lulu/pei_data.c
View File

@ -7,10 +7,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
/* One installed DIMM per channel -- can be changed by SPD init */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
/* P0: Port B, CN01 (IOBoard) */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_BACK_PANEL);
/* P1: Port A, CN01 */

4
src/mainboard/google/auron/variants/samus/pei_data.c
View File

@ -20,10 +20,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->ec_present = 1;
/* One installed DIMM per channel */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));

2
src/mainboard/google/jecht/spd/spd.c
View File

@ -8,8 +8,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
{
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
// Enable 2x refresh mode
pei_data->ddr_refresh_2x = 1;
pei_data->dq_pins_interleaved = 1;

3
src/mainboard/intel/wtm2/pei_data.c
View File

@ -6,9 +6,6 @@
void mainboard_fill_spd_data(struct pei_data *pei_data)
{
/* One installed DIMM per channel */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
pei_data->spd_addresses[0] = 0xa2;
pei_data->spd_addresses[2] = 0xa2;
}

1
src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c
View File

@ -6,7 +6,6 @@
void mainboard_fill_spd_data(struct pei_data *pei_data)
{
/* One DIMM slot */
pei_data->dimm_channel1_disabled = 3;
pei_data->spd_addresses[0] = 0xa0;
}

3
src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c
View File

@ -8,9 +8,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
pei_data->dq_pins_interleaved = 1;
/* One DIMM slot */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
}

2
src/soc/intel/broadwell/include/soc/pei_wrapper.h
View File

@ -26,6 +26,8 @@ static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
pei_data->usb3_ports[port].fixed_eq = fixed_eq;
}
#define SPD_MEMORY_DOWN 0xff
void broadwell_fill_pei_data(struct pei_data *pei_data);
void mainboard_fill_pei_data(struct pei_data *pei_data);
void mainboard_fill_spd_data(struct pei_data *pei_data);

20
src/soc/intel/broadwell/raminit.c
View File

@ -177,6 +177,17 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
}
}
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
{
return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
}
void perform_raminit(const struct chipset_power_state *const power_state)
{
const int s3resume = power_state->prev_sleep_state == ACPI_S3;
@ -186,6 +197,15 @@ void perform_raminit(const struct chipset_power_state *const power_state)
mainboard_fill_pei_data(&pei_data);
mainboard_fill_spd_data(&pei_data);
/* Calculate unimplemented DIMM slots for each channel */
pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
for (size_t i = 0; i < ARRAY_SIZE(pei_data.spd_addresses); i++) {
const uint8_t addr = pei_data.spd_addresses[i];
pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0 : addr;
}
post_code(0x32);
timestamp_add_now(TS_INITRAM_START);