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Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names 

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs 2010-12-26 05:16:47 +00:00 committed by Peter Stuge
parent 1c6d4e6055
commit 3344743215
3 changed files with 20 additions and 15 deletions
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18
src/cpu/amd/model_gx2/cpureginit.c
View File

@ -15,25 +15,25 @@ void cpuRegInit (void)
wrmsr(msrnum, msr);
/* Set up GLCP to grab BTM data. */
msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR */
msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */
msr.hi = 0x0;
msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out, */
wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */
/* Turn off debug clock */
msrnum = 0x04C000016; /* DBG_CLK_CTL */
msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */
msr.lo = 0x00; /* No clock */
msr.hi = 0x00;
wrmsr(msrnum, msr);
/* Set debug clock to CPU */
msrnum = 0x04C000016; /* DBG_CLK_CTL */
msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */
msr.lo = 0x01; /* CPU CLOCK */
msr.hi = 0x00;
wrmsr(msrnum, msr);
/* Set fifo ctl to BTM bits wide */
msrnum = 0x04C00005E; /* FIFO_CTL */
msrnum = GLCP_FIFOCTL; /* FIFO_CTL */
msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit) */
wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0) */
/* Bit [19] sets it up in slow data mode. */
@ -53,7 +53,7 @@ void cpuRegInit (void)
/* Set up delay on data lines, so that the hold time */
/* is 1 ns. */
msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS */
msrnum = GLCP_PROCSTAT; /* GLCP IO DELAY CONTROLS */
msr.lo = 0x082b5ad68;
msr.hi = 0x080ad6b57; /* RGB delay = 0x07 */
wrmsr(msrnum, msr);
@ -64,7 +64,7 @@ void cpuRegInit (void)
msr.hi = 0;
wrmsr(msrnum, msr);
msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR */
msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */
msr.hi = 0x0;
msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */
wrmsr(msrnum, msr);
@ -85,7 +85,7 @@ void cpuRegInit (void)
wrmsr(msrnum, msr);
/* Setup throttling to proper mode if it is ever enabled. */
msrnum = 0x04C00001E;
msrnum = GLCP_TH_OD;
msr.hi = 0x000000000;
msr.lo = 0x00000603C;
wrmsr(msrnum, msr);
@ -108,14 +108,14 @@ void cpuRegInit (void)
wrmsr(msrnum, msr);
/* Enable RSDC */
msrnum = 0x1301 ;
msrnum = CPU_AC_SMM_CTL;
msr = rdmsr(msrnum);
msr.lo |= 0x08;
wrmsr(msrnum, msr);
/* Enable BTB */
/* I hate to put this check here but it doesn't really work in cpubug.asm */
msrnum = MSR_GLCP+0x17;
msrnum = GLCP_CHIP_REVID;
msr = rdmsr(msrnum);
if (msr.lo >= CPU_REV_2_1){
msrnum = CPU_PF_BTB_CONF;

13
src/include/cpu/amd/gx2def.h
View File

@ -15,10 +15,15 @@
#define CPU_REV_2_2 0x022
#define CPU_REV_3_0 0x030
/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
#define GLCP_CLK_DIS_DELAY 0x4c000008
#define GLCP_PMCLKDISABLE 0x4c000009
#define GLCP_CHIP_REVID 0x4c000017
/* GeodeLink Control Processor Registers, GLIU1, Port 3 ; MSR_GLCP = 4c00xxxx */
#define GLCP_CLK_DIS_DELAY (MSR_GLCP + 0x08)
#define GLCP_PMCLKDISABLE (MSR_GLCP + 0x09)
#define GLCP_DBGOUT (MSR_GLCP + 0x0C)
#define GLCP_PROCSTAT (MSR_GLCP + 0x0D)
#define GLCP_DBGCLKCTL (MSR_GLCP + 0x16)
#define GLCP_CHIP_REVID (MSR_GLCP + 0x17)
#define GLCP_TH_OD (MSR_GLCP + 0x1E)
#define GLCP_FIFOCTL (MSR_GLCP + 0x5E)
/* GLCP_SYS_RSTPLL, Upper 32 bits */
#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9

4
src/northbridge/amd/gx2/northbridge.c
View File

@ -29,8 +29,8 @@ int sizeram(void)
unsigned short dimm;
/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
msr = rdmsr(0x20000018);
printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo);
msr = rdmsr(MC_CF07_DATA);
printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
/* dimm 0 */
dimm = msr.hi;