nb/intel/haswell: Add support for PEG
This means that any PCIe device placed in a PEG slot should now work. During S3 resume, link training sometimes does not complete before device enumeration. However, no tangible issues have been observed. Fixing it would introduce a rather large delay in S3 resume. There are a few minor shortcomings: - Using PEG for display output is not yet supported. - Only PEG2 is supported. An extra (unknown) training sequence is said to be needed for PEG3. - The ACPI _PRT method is not yet generated, so legacy interrupt routing doesn't work for devices with multiple functions. Tested on an ASRock H81M-HDS. Using a Radeon HD 6450 graphics card works under GNU/Linux, with PRIME [1]. An x1 PCIe card was also tested in the PEG slot, and it appears functional. [1]: https://wiki.archlinux.org/index.php/PRIME Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -143,6 +143,8 @@ void romstage_common(const struct romstage_params *params)
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#endif
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}
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haswell_unhide_peg();
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setup_sdram_meminfo(params->pei_data);
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romstage_handoff_init(wake_from_s3);
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@ -19,9 +19,12 @@
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <elog.h>
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#include "haswell.h"
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static bool peg_hidden[3];
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static void haswell_setup_bars(void)
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{
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printk(BIOS_DEBUG, "Setting up static northbridge registers...");
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@ -45,13 +48,13 @@ static void haswell_setup_bars(void)
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printk(BIOS_DEBUG, " done.\n");
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}
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static void haswell_setup_graphics(void)
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static void haswell_setup_igd(void)
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{
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bool igd_enabled;
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u16 ggc;
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u8 reg8;
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printk(BIOS_DEBUG, "Initializing Graphics...\n");
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printk(BIOS_DEBUG, "Initializing IGD...\n");
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igd_enabled = !!(pci_read_config32(PCI_DEV(0, 0, 0), DEVEN)
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& DEVEN_D2EN);
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@ -79,6 +82,66 @@ static void haswell_setup_graphics(void)
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pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8);
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}
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static void start_peg2_link_training(const pci_devfn_t dev)
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{
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u32 mask;
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switch (dev) {
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case PCI_DEV(0, 1, 2):
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mask = DEVEN_D1F2EN;
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break;
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case PCI_DEV(0, 1, 1):
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mask = DEVEN_D1F1EN;
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break;
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case PCI_DEV(0, 1, 0):
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mask = DEVEN_D1F0EN;
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break;
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default:
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printk(BIOS_ERR, "Link training tried on a non-PEG device!\n");
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return;
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}
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pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
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printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(dev));
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/*
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* The PEG device is hidden while the MRC runs. This is because the
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* MRC makes configurations that are not ideal if it sees a VGA
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* device in a PEG slot, and it locks registers preventing changes
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* to these configurations.
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*/
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pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0);
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peg_hidden[PCI_FUNC(dev)] = true;
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printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(dev));
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}
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void haswell_unhide_peg(void)
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{
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u32 deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
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for (u8 fn = 0; fn <= 2; fn++) {
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if (peg_hidden[fn]) {
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deven |= DEVEN_D1F0EN >> fn;
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peg_hidden[fn] = false;
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printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn);
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}
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}
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pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven);
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}
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static void haswell_setup_peg(void)
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{
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u32 deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
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if (deven & DEVEN_D1F2EN)
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start_peg2_link_training(PCI_DEV(0, 1, 2));
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if (deven & DEVEN_D1F1EN)
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start_peg2_link_training(PCI_DEV(0, 1, 1));
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if (deven & DEVEN_D1F0EN)
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start_peg2_link_training(PCI_DEV(0, 1, 0));
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}
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static void haswell_setup_misc(void)
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{
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u32 reg32;
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@ -140,7 +203,8 @@ void haswell_early_initialization(int chipset_type)
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/* Setup IOMMU BARs */
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haswell_setup_iommu();
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haswell_setup_graphics();
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haswell_setup_peg();
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haswell_setup_igd();
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haswell_setup_misc();
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}
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@ -221,6 +221,7 @@ void intel_northbridge_haswell_finalize_smm(void);
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void haswell_early_initialization(int chipset_type);
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void haswell_late_initialization(void);
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void set_translation_table(int start, int end, u64 base, int inc);
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void haswell_unhide_peg(void);
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/* debugging functions */
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void print_pci_devices(void);
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