From 335384d2b75eb0266c6f13b52e20b2d3bba390ea Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Sun, 22 Mar 2020 22:27:44 -0700 Subject: [PATCH] soc/intel/xeon_sp: Configure P2SB BAR in bootblock In order to use early serial output we need to enable P2SB BAR0, because that allows PCR access to PCH registers. TEST=tested on OCP Tioga Pass Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/bootblock.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 453c383897..8e236f2942 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -21,6 +21,7 @@ #include #include #include +#include const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -54,6 +55,11 @@ void bootblock_soc_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); pch_enable_lpc(); + + /* Set up P2SB BAR. This is needed for PCR to work */ + uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND); + pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); + pci_mmio_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); } void bootblock_soc_init(void)