lib: Add library to handle SPD data in CBFS or DIMM
Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Naresh G Solanki
Aaron Durbin
parent
500ba45b2c
commit
335781ad53
25
src/Kconfig
25
src/Kconfig
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@ -316,6 +316,31 @@ config GENERIC_GPIO_LIB
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implies configurability usually found on SoCs, particularly the
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ability to control internal pull resistors.
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config GENERIC_SPD_BIN
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bool
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default n
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help
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If enabled, add support for adding spd.hex files in cbfs as spd.bin
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and locating it runtime to load SPD. Additionally provide provision to
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fetch SPD over SMBus.
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config DIMM_MAX
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int
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default 2
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depends on GENERIC_SPD_BIN
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help
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Total number of memory DIMM slots available on motherboard.
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It is multiplication of number of channel to number of DIMMs per
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channel
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config DIMM_SPD_SIZE
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int
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default 256
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depends on GENERIC_SPD_BIN
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help
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Total SPD size that will be used for DIMM.
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Ex: DDR3 256, DDR4 512.
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config BOARD_ID_AUTO
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bool
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default n
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@ -0,0 +1,57 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SPD_BIN_H
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#define SPD_BIN_H
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#include <arch/early_variables.h>
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#include <stdint.h>
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#include <commonlib/region.h>
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#define SPD_PAGE_LEN 256
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#define SPD_PAGE_LEN_DDR4 512
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#define SPD_PAGE_0 (0x6C >> 1)
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#define SPD_PAGE_1 (0x6E >> 1)
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0B
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#define SPD_DRAM_LPDDR3_INTEL 0xF1
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#define SPD_DRAM_LPDDR3_JEDEC 0x0F
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#define SPD_DRAM_DDR4 0x0C
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_ORGANIZATION 7
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#define SPD_BUS_DEV_WIDTH 8
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#define DDR3_SPD_PART_OFF 128
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#define DDR3_SPD_PART_LEN 18
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#define LPDDR3_SPD_PART_OFF 128
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#define LPDDR3_SPD_PART_LEN 18
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#define DDR4_SPD_PART_OFF 329
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#define DDR4_SPD_PART_LEN 20
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#define LPDDR4_SPD_PART_OFF 329
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#define LPDDR4_SPD_PART_LEN 20
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struct spd_block {
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u8 *spd_array[CONFIG_DIMM_MAX];
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/* Length of each dimm */
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u16 len;
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};
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void print_spd_info(uint8_t spd[]);
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/* Return 0 on success & -1 on failure */
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int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index);
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void dump_spd_info(struct spd_block *blk);
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void get_spd_smbus(struct spd_block *blk);
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#endif
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@ -279,3 +279,21 @@ subdirs-y += ../../3rdparty/libhwbase
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ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb
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endif # CONFIG_RAMSTAGE_LIBHWBASE
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romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c
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LIB_SPD_BIN = $(obj)/spd.bin
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LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd ROM data
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$(LIB_SPD_BIN): $(LIB_SPD_DEPS)
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for f in $(LIB_SPD_DEPS); \
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do for c in $$(cat $$f | grep -v ^#); \
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do printf $$(printf '\%o' 0x$$c); \
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done; \
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done > $@
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cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin
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spd.bin-file := $(LIB_SPD_BIN)
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spd.bin-type := spd
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@ -0,0 +1,168 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/byteorder.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <spd_bin.h>
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#include <string.h>
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#include <device/early_smbus.h>
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static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL;
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void dump_spd_info(struct spd_block *blk)
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{
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u8 i;
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for (i = 0; i < CONFIG_DIMM_MAX; i++)
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if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) {
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printk(BIOS_DEBUG, "SPD @ 0x%02X\n", 0xA0|(i << 1));
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print_spd_info(blk->spd_array[i]);
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}
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}
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void print_spd_info(uint8_t spd[])
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{
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const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
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const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 };
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const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
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const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
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const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
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const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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char spd_name[DDR4_SPD_PART_LEN+1] = { 0 };
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int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
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int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
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int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
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int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
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int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
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int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
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int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
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/* Module type */
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printk(BIOS_INFO, "SPD: module type is ");
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switch (spd[SPD_DRAM_TYPE]) {
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case SPD_DRAM_DDR3:
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printk(BIOS_INFO, "DDR3\n");
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/* Module Part Number */
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memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN);
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spd_name[DDR3_SPD_PART_LEN] = 0;
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break;
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case SPD_DRAM_LPDDR3_INTEL:
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case SPD_DRAM_LPDDR3_JEDEC:
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printk(BIOS_INFO, "LPDDR3\n");
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/* Module Part Number */
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memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF],
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LPDDR3_SPD_PART_LEN);
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spd_name[LPDDR3_SPD_PART_LEN] = 0;
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break;
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case SPD_DRAM_DDR4:
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printk(BIOS_INFO, "DDR4\n");
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memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN);
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spd_name[DDR4_SPD_PART_LEN] = 0;
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ranks = (spd[SPD_ORGANIZATION] >> 3) & 7;
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devw = spd_devw[spd[12] & 7];
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busw = spd_busw[spd[13] & 7];
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break;
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default:
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printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
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break;
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}
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printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
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printk(BIOS_INFO,
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"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
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banks, ranks, rows, cols, capmb);
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printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
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devw, busw);
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if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
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/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
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printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
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capmb / 8 * busw / devw * ranks);
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}
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}
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static void update_spd_len(struct spd_block *blk)
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{
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u8 i, j = 0;
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for (i = 0 ; i < CONFIG_DIMM_MAX; i++)
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if (blk->spd_array[i] != NULL)
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j |= blk->spd_array[i][SPD_DRAM_TYPE];
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/* If spd used is DDR4, then its length is 512 byte. */
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if (j == SPD_DRAM_DDR4)
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blk->len = SPD_PAGE_LEN_DDR4;
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else
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blk->len = SPD_PAGE_LEN;
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}
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int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index)
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{
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struct cbfsf fh;
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uint32_t cbfs_type = CBFS_TYPE_SPD;
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cbfs_boot_locate(&fh, "spd.bin", &cbfs_type);
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cbfs_file_data(spd_rdev, &fh);
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return rdev_chain(spd_rdev, spd_rdev, spd_index * CONFIG_DIMM_SPD_SIZE,
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CONFIG_DIMM_SPD_SIZE);
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}
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static void get_spd(u8 *spd, u8 addr)
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{
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u16 i;
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/* Assuming addr is 8 bit address, make it 7 bit */
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addr = addr >> 1;
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if (smbus_read_byte(0, addr, 0) == 0xff) {
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printk(BIOS_INFO, "No memory dimm at address %02X\n",
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addr << 1);
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/* Make sure spd is zeroed if dimm doesn't exist. */
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memset(spd, 0, CONFIG_DIMM_SPD_SIZE);
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return;
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}
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for (i = 0; i < SPD_PAGE_LEN; i++)
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spd[i] = smbus_read_byte(0, addr, i);
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/* Check if module is DDR4, DDR4 spd is 512 byte. */
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if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 &&
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CONFIG_DIMM_SPD_SIZE >= SPD_DRAM_DDR4) {
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/* Switch to page 1 */
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smbus_write_byte(0, SPD_PAGE_1, 0, 0);
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for (i = 0; i < SPD_PAGE_LEN; i++)
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spd[i+SPD_PAGE_LEN] = smbus_read_byte(0, addr, i);
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/* Restore to page 0 */
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smbus_write_byte(0, SPD_PAGE_0, 0, 0);
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}
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}
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void get_spd_smbus(struct spd_block *blk)
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{
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u8 i, j;
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unsigned char *spd_data_ptr = car_get_var_ptr(&spd_data);
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for (i = 0 ; i < CONFIG_DIMM_MAX; i++) {
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get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE,
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0xA0 + (i << 1));
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blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE;
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}
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for (j = i; j < CONFIG_DIMM_MAX; j++)
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blk->spd_array[j] = NULL;
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update_spd_len(blk);
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}
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