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soc/amd/sabrina/include/gpio: add I3C3 IOMUX definitions 

According to PPR #57243 version 1.56, the IOMUX setting 2 of the pins 19
and 20 is the I3C3 controller and not the I2C3 controller.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9688f1816aa840c64441495ed451997a474b306f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-03-31 01:21:20 +02:00
parent b4e3408967
commit 3363db0173
1 changed files with 2 additions and 2 deletions
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4
src/soc/amd/sabrina/include/soc/gpio.h
View File

@ -148,11 +148,11 @@
#define GPIO_18_IOMUX_GPIOxx 1
#define GPIO_19_IOMUX_SMBUS1_SCL 0
#define GPIO_19_IOMUX_I2C3_SCL 1
/* GPIO 19 IOMUX == 2 is also I2C3_SCL */
#define GPIO_19_IOMUX_I3C3_SCL 2
#define GPIO_19_IOMUX_GPIOxx 3
#define GPIO_20_IOMUX_SMBUS1_SDA 0
#define GPIO_20_IOMUX_I2C3_SDA 1
/* GPIO 19 IOMUX == 2 is also I2C3_SDA */
#define GPIO_20_IOMUX_I3C3_SDA 2
#define GPIO_20_IOMUX_GPIOxx 3
#define GPIO_21_IOMUX_ESPI_RESET_L 0
#define GPIO_21_IOMUX_KBRST_L 1