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nb/intel/gm45: Drop casts from DEFAULT_{MCHBAR,DMIBAR} 

There's no need to wrap these macros with casts. Removing them allows
dropping `uintptr_t` casts in other files. Changes the binary, though.

Change-Id: I1553cbeee45972d6deba8cb9969c69fceeb19574
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45432
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-09-15 14:30:13 +02:00
parent e60155ff13
commit 3378de12f6
3 changed files with 5 additions and 9 deletions
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4
src/northbridge/intel/gm45/early_init.c
View File

@ -9,10 +9,10 @@ void gm45_early_init(void)
const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */ /* Setup MCHBAR. */
pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
/* Setup DMIBAR. */ /* Setup DMIBAR. */
pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
/* Setup EPBAR. */ /* Setup EPBAR. */
pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);

6
src/northbridge/intel/gm45/gm45.h
View File

@ -170,13 +170,8 @@ enum {
#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes #define CMOS_WRITE_TRAINING 0x90 /* 16 bytes
(could be reduced to 10 bytes) */ (could be reduced to 10 bytes) */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed14000)
#define DEFAULT_DMIBAR ((u8 *)0xfed18000)
#else
#define DEFAULT_MCHBAR 0xfed14000 #define DEFAULT_MCHBAR 0xfed14000
#define DEFAULT_DMIBAR 0xfed18000 #define DEFAULT_DMIBAR 0xfed18000
#endif
#define DEFAULT_EPBAR 0xfed19000 #define DEFAULT_EPBAR 0xfed19000
#define DEFAULT_HECIBAR ((u8 *)0xfed1a000) #define DEFAULT_HECIBAR ((u8 *)0xfed1a000)
@ -356,6 +351,7 @@ enum {
#define CxDTAEW(x) (0x1280+(x*0x100)) #define CxDTAEW(x) (0x1280+(x*0x100))
#define CxDTC(x) (0x1288+(x*0x100)) #define CxDTC(x) (0x1288+(x*0x100))
/* /*
* DMIBAR * DMIBAR
*/ */

4
src/northbridge/intel/gm45/pcie.c
View File

@ -250,7 +250,7 @@ static void setup_rcrb(const int peg_enabled)
/* Link1: component ID 1, link valid. */ /* Link1: component ID 1, link valid. */
EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0); EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0);
EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; EPBAR32(EPLE1A) = DEFAULT_DMIBAR;
if (peg_enabled) if (peg_enabled)
/* Link2: link_valid. */ /* Link2: link_valid. */
@ -268,7 +268,7 @@ static void setup_rcrb(const int peg_enabled)
/* Link2: component ID 1 (MCH), link valid */ /* Link2: component ID 1 (MCH), link valid */
DMIBAR32(DMILE2D) = DMIBAR32(DMILE2D) =
(DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0); (DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0);
DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR; DMIBAR32(DMILE2A) = DEFAULT_MCHBAR;
} }
void gm45_late_init(const stepping_t stepping) void gm45_late_init(const stepping_t stepping)