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mb/google/zork: update USB 2.0 controller Lane Parameter for dirinboz 

Enhance USB 2.0 M/B C0, DB C1 A1 port:
HS DC Voltage Level(TXVREFTUNE0): 0xe
COMPDISTUNE(COMPDISTUNE0): 0x7

BUG=b:165209698
BRANCH=zork
TEST=emerge-zork coreboot

Change-Id: I371e4295c2ee161096f0a277c0c649bf217269b2
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kevin Chiu 2020-11-23 13:01:35 +08:00 committed by Martin Roth
parent bc148df898
commit 3379879c6c
1 changed files with 39 additions and 0 deletions
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39
src/mainboard/google/zork/variants/dirinboz/overridetree.cb
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@ -21,6 +21,45 @@ chip soc/amd/picasso
register "telemetry_vddcr_soc_offset" = "167"
# End : OPN Performance Configuration
# USB 2.0 strength
register "usb_2_port_tune_params[0]" = "{
.com_pds_tune = 0x07,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.tx_vref_tune = 0xe,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# USB 2.0 strength
register "usb_2_port_tune_params[2]" = "{
.com_pds_tune = 0x07,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.tx_vref_tune = 0xe,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# USB 2.0 strength
register "usb_2_port_tune_params[3]" = "{
.com_pds_tune = 0x07,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.tx_vref_tune = 0xe,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# I2C2 for touchscreen and trackpad
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,