From 337f8a173321a397011465644feaa613891e8478 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Mon, 16 Jan 2023 11:42:35 +0800 Subject: [PATCH] soc/intel/xeon_sp: Remove NO_FSP_TEMP_RAM_EXIT from common config For SPR-SP FSP MRC cache, NO_FSP_TEMP_RAM_EXIT should not be selected. Change-Id: I63101f286809d6cebb9a7d74443446cb3fe650c4 Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/71928 Reviewed-by: Simon Chou Reviewed-by: Jonathan Zhang Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/soc/intel/xeon_sp/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 16864796bb..0196e6d313 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -11,6 +11,7 @@ config SOC_INTEL_SKYLAKE_SP bool select XEON_SP_COMMON_BASE select PLATFORM_USES_FSP2_0 + select NO_FSP_TEMP_RAM_EXIT help Intel Skylake-SP support @@ -19,6 +20,7 @@ config SOC_INTEL_COOPERLAKE_SP select XEON_SP_COMMON_BASE select PLATFORM_USES_FSP2_2 select CACHE_MRC_SETTINGS + select NO_FSP_TEMP_RAM_EXIT help Intel Cooper Lake-SP support @@ -38,7 +40,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select INTEL_CAR_NEM # For postcar only now select INTEL_DESCRIPTOR_MODE_CAPABLE - select NO_FSP_TEMP_RAM_EXIT select PARALLEL_MP_AP_WORK select PMC_GLOBAL_RESET_ENABLE_LOCK select POSTCAR_STAGE