From 338c8002d2a2d4335b9ebf0e5bcc5b3ca1ce35a4 Mon Sep 17 00:00:00 2001 From: praveen hodagatta pranesh Date: Fri, 21 Sep 2018 04:24:16 +0800 Subject: [PATCH] soc/intel/cannonlake: Correct ITSS port id. According to cannon lake PCH BIOS specification document #570374 target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2. BUG=None TEST=None Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494 Signed-off-by: praveen hodagatta pranesh Reviewed-on: https://review.coreboot.org/28698 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Lijian Zhao Reviewed-by: Kin Wai Ng --- src/soc/intel/cannonlake/include/soc/pcr_ids.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h index 891b18742b..c4a18e8f90 100644 --- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h +++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h @@ -35,7 +35,7 @@ #define PID_PSF4 0xbd #define PID_SCS 0xc0 #define PID_RTC 0xc3 -#define PID_ITSS 0xc2 +#define PID_ITSS 0xc4 #define PID_LPC 0xc7 #define PID_SERIALIO 0xcb