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soc/intel/common: Add support to clear GPI IS & IE registers 

Add support to reset the GPI Interrupt Status & Enable registers so that
the system does not experience any interrupt storm from a GPI when it
comes out of one of the sleep states.

BUG=b:130593883
BRANCH=None
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up. Ensure that the system boots fine to ChromeOS.

Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2019-04-24 10:12:38 -06:00 committed by Patrick Georgi
parent c126084bc5
commit 3391a31cf9
2 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
src/soc/intel/common/block/gpio/gpio.c
View File

@ -62,6 +62,10 @@
((group) * sizeof(uint32_t)))
#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \
((group) * sizeof(uint32_t)))
#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \
((group) * sizeof(uint32_t)))
#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \
((group) * sizeof(uint32_t)))
static inline size_t relative_pad_in_comm(const struct pad_community *comm,
gpio_t gpio)
@ -582,3 +586,26 @@ uint32_t __weak soc_gpio_pad_config_fixup(const struct pad_config *cfg,
{
return reg_val;
}
void gpi_clear_int_cfg(void)
{
int i, group, num_groups;
uint32_t sts_value;
size_t gpio_communities;
const struct pad_community *comm;
comm = soc_gpio_get_community(&gpio_communities);
for (i = 0; i < gpio_communities; i++, comm++) {
num_groups = comm->num_gpi_regs;
for (group = 0; group < num_groups; group++) {
/* Clear the enable register */
pcr_write32(comm->port, GPI_IE_OFFSET(comm, group), 0);
/* Read and clear the set status register bits*/
sts_value = pcr_read32(comm->port,
GPI_IS_OFFSET(comm, group));
pcr_write32(comm->port,
GPI_IS_OFFSET(comm, group), sts_value);
}
}
}

6
src/soc/intel/common/block/include/intelblocks/gpio.h
View File

@ -209,5 +209,11 @@ uint8_t gpio_get_pad_portid(const gpio_t pad);
uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
int dw_reg, uint32_t reg_val);
/*
* Function to reset/clear the GPI Interrupt Enable & Status registers for
* all GPIO pad communities.
*/
void gpi_clear_int_cfg(void);
#endif
#endif /* _SOC_INTELBLOCKS_GPIO_H_ */